Staff Analog Mixed-Signal Design Engineer (f/m/div) - Pavia (Italy), Italy
$43,440 - $59,730 USD yearly
Originally posted 26 June 2026 by the employer — open 76 days.
About the role
This Staff Analog Mixed-Signal Design Engineer role focuses on the design and verification of analog circuits for high-speed SerDes sub-blocks.
What you'll do
- Design and verify analog circuits for high-speed SerDes sub-blocks, including de-/serializers, current and voltage-mode drivers, Continuous-Time Linear Equalizers (CTLE), and Slicers.
- Perform analog sign-off activities, including EMI, aging, and other reliability checks.
- Collaborate with System Architecture teams to define and refine specifications for analog sub-blocks.
- Partner with Digital Design teams to ensure effective control and integration of analog blocks.
- Work closely with Analog Physical Design teams to achieve robust layout implementation for high-frequency critical blocks.
- Engage with Verification teams to ensure high-quality, reliable, and silicon-ready designs.
What you'll need
- Master’s degree in Electrical/Electronic Engineering or a related field of study.
- 5+ years of experience in analog design for high-speed SerDes IPs.
- Knowledge of SerDes sub-block design, including de-/serializers, current and voltage-mode drivers, Continuous-Time Linear Equalizers (CTLE), slicers, and related circuits.
- Experience with Analog Design Tools (e.g., Virtuoso, Spectre, and others).
- Fluency in English (mandatory).
Skills: high-speed SerDes, de-/serializers, CTLE, Slicers, analog sub-blocks
This role has been open 76 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 5 | 217 |
| Median days open | 76 d | 91 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed SerDes, de-/serializers, CTLE, Slicers, analog sub-blocks
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.