Staff Analog IC Layout Engineer (Block & Chip) - San Diego, California, United States
$145,000 - $175,000 USD yearly
Originally posted 3 September 2026 by the employer — open 7 days.
About the role
As a Staff Analog Layout Engineer, you will take technical ownership of the physical layout and verification of complex analog and mixed-signal integrated circuits for the ATE market. This role involves working with advanced process technologies ranging from 65nm CMOS to 100+V BCD.
What you'll do
- Perform physical layout of analog and mixed-signal integrated circuits at both the block and full-chip level.
- Develop floorplans and optimize component placement for area, performance, and power.
- Perform LVS and DRC verification to ensure layout accuracy and compliance with process design rules.
- Collaborate with design engineers to translate circuit requirements into high-quality physical layouts.
- Partner with digital design, packaging, and other cross-functional teams to optimize overall chip performance.
- Troubleshoot and resolve layout, verification, and manufacturability issues.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field.
- Minimum of 8 years of professional experience in analog and mixed-signal IC layout design.
- Strong understanding of analog CMOS circuits and device physics.
- Solid knowledge of the IC design, qualification, and manufacturing lifecycle.
- Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner.
- Proficiency in LVS and DRC verification using Cadence or Mentor tools.
Skills: physical layout, analog and mixed-signal ICs, floorplans, LVS and DRC verification, Cadence EDA tools
This role has been open 6 days — below the 14-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
30
|
Median days open
14 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Elevate Semiconductor | All employers we track in this specialty (30 roles · 19 employers) |
|---|---|---|
| Open roles in category | 1 | 30 |
| Median days open | 6 d | 14 d (−8 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: physical layout, analog and mixed-signal ICs, floorplans, LVS and DRC verification, Cadence EDA tools
Who's hiring in this category
- Celero · 4 open roles · median 1 d
- Infineon Technologies · 3 open roles · median 29 d
- QORVO · 3 open roles · median 13 d
- Marvell Technology · 2 open roles · median 5 d
- Monolithic Power Systems · 2 open roles · median 15 d
- onsemi · 2 open roles · median 15 d
How we counted: 30 open Analog IC Design (Analog Layout) roles from 19 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.