Staff Analog Design Engineer, TX/RX Datapath - Santa Clara, United States
Originally posted 19 August 2026 by the employer — open 22 days.
This role focuses on the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet.
About the role
This role involves owning the transmit and receive datapath of a high-speed SerDes. This role is a hands-on, transistor-level design position focused on d-Matrix's IO chiplet.
What you'll do
- Own transistor-level design of the SerDes transmit path, including output drivers (SST and/or CML), pre-driver, and serializer stages.
- Own transistor-level design of the receive front-end, including termination, ESD-aware input network, CTLE, VGA, samplers, and ADC-based front-ends.
- Design and verify the equalization path (DFE and FFE architecture, tap resolution, adaptation behavior) and conduct trade studies for architecture selection.
- Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets.
- Build verification environments for blocks, including testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation.
- Perform link and channel modeling in MATLAB, Python, or equivalent, including S-parameter channel and package models, statistical eye and BER analysis.
- Drive layout of blocks in deep sub-micron nodes, collaborating with layout engineers on floorplan, matching, shielding, current density, and parasitic control.
- Contribute to testboard design, silicon bring-up, and bench characterization, correlating measured performance against simulation.
What you'll need
- BS/MS/PhD in Electrical Engineering with 8+ years of hands-on analog and mixed-signal circuit design experience.
- Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link.
- Deep knowledge of high-speed driver design, receive front-end design, and equalization.
- Practical command of jitter and noise analysis, including decomposition, budgeting, and simulation methodology.
- Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools (Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation).
- Experience with link/channel modeling (MATLAB, Python, S-parameter models).
- Silicon bring-up and bench debug experience with high-speed lab equipment (scopes, BERTs).
Nice to have
- Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), including short-reach, low-energy-per-bit links.
- PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends.
- Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.
- Experience porting a datapath block across process nodes.
- IBIS-AMI model generation, or SerDes ATE and production test development.
- Participation in or contribution to standards bodies.
Skills: SerDes, transmit path, receive front-end, equalization, transistor-level design, link modeling
This role has been open 22 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | d-Matrix | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 4 | 1317 · 100 employers |
| Median days open | 22 d | 91 d (−69 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes, transmit path, receive front-end, equalization, transistor-level design, link modeling
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.