Staff Analog Design Engineer, SerDes Clocking - Santa Clara, United States

Originally posted 19 August 2026 by the employer.

This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet.

About the role

This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet. This role involves carrying designs from specification through silicon characterization, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro.

What you'll do

• Own transistor-level design of low-jitter frequency synthesis, including LC and/or ring PLL, loop filter, charge pump or digital loop, VCO, and divider chain.
• Own the phase interpolator and phase rotation scheme, considering INL/DNL, glitch behavior, and interpolation resolution.
• Design high-frequency clock distribution across the SerDes macro, including buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation.
• Define and verify CDR architecture and loop dynamics, modeling loop behavior in MATLAB, Python, or equivalent, and correlating against transistor-level and silicon results.
• Build phase-noise and jitter budgets for the link and own the analysis showing where jitter originates.
• Build the verification environment for your blocks, including PSS/HB and transient noise analysis, PVT corner coverage, Monte Carlo, and post-layout back-annotated simulation, and provide behavioral and Verilog-A models for full-chip verification.
• Drive layout of your blocks in deep sub-micron nodes, with particular attention to inductor and VCO layout, shielding, symmetry, and supply/substrate isolation.
• Take your blocks through silicon bring-up and bench characterization, correlating measured results against simulation.

What you'll need

• BS/MS/PhD in Electrical Engineering, with 5+ years of hands-on analog and mixed-signal circuit design experience.
• Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link.
• Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory.
• Working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer.
• Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation.
• Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation).
• Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs.

Nice to have

• Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including clocking architecture choices specific to short-reach, low-energy-per-bit links.
• Forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR.
• Digital and hybrid PLL/CDR implementations, including the digital calibration around them.
• Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.
• Experience porting a clocking block across process nodes.
• Participation in or contribution to standards bodies.

Skills: SerDes, PLL, CDR, jitter, phase interpolator, transistor-level design