St Staff Engineer, Power Delivery - Austin, Texas, United States of America, United States
$191,800 - $287,800 USD yearly
Originally posted 25 October 2026 by the employer.
About the role
This role defines, develops, and optimizes on-chip power delivery network (PDN) and power-grid architectures for advanced-node, high-performance SoCs. You will focus on power-grid topology, PDN-aware floorplanning, on-die decoupling, bump connectivity, IR drop, dynamic voltage droop, and electromigration across high-current CPU, NSP, and GPU IPs.
What you'll do
- Own on-chip power delivery network architecture and power-grid strategy for advanced-node, high-performance SoCs. - Define and optimize power-grid topology, rail structure, power domains, and distribution for CPU, NSP, GPU, and other performance-critical IPs. - Drive PDN-aware floorplanning with SoC Physical Design and IP teams to balance power delivery against PPA, routing resources, timing, and implementation constraints. - Establish static IR-drop, dynamic voltage-droop, impedance, EM/current-density, and reliability budgets, driving analyses to achieve power-integrity closure. - Define on-die decoupling-capacitance strategies, bump connectivity, and allocation across on-die PG and package PDN interfaces. - Define the on-chip PG roadmap for advanced technology nodes, including evaluation and tradeoff analysis of front-side and backside power delivery.
What you'll need
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related field with 6+ years of System/Package Design/Technology Engineering experience (or Master's with 5+ years, or PhD with 4+ years). - Experience with on-chip power-grid architecture, static IR drop, dynamic voltage droop, and electromigration (EM) analysis. - Experience in PDN-aware floorplanning and die-to-package power delivery integration.
Nice to have
- Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or related field with a focus on power integrity, VLSI, physical design, or semiconductor power delivery. - Experience with Cadence Voltus, Sigrity PowerSI, Ansys HFSS, Q3D, SiWave, HSpice, ADS, or equivalent power-integrity and circuit-simulation tools. - Experience developing or improving PDN extraction, modeling, analysis, automation, and signoff methodologies. - Knowledge of advanced power-grid technologies, backside power delivery, advanced packaging, and die-to-package power-delivery co-optimization. - Scripting and automation experience using Python, TCL, or similar languages.
Skills: Power Delivery Network, IR-drop, EM, Power Integrity, Voltus, Floorplanning
This role has been open 0 days — well below the 65-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 673 |
| Open roles in the wider Physical Implementation family | 170 | 1491 · 109 employers |
| Median days open | 48 d | 65 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Power Delivery Network, IR-drop, EM, Power Integrity, Voltus, Floorplanning
Who's hiring in this category
- Qualcomm (this employer) · 124 open roles · median 48 d
- AMD · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 17 d
- Synopsys · 37 open roles · median 39 d
- NVIDIA · 36 open roles · median 67 d
- Broadcom · 35 open roles · median 104 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.