Principal Physical Verification Engineer - USA-CA San Jose Innovation Drive, United States
$143,800 - $230,000 USD yearly
Originally posted 24 October 2026 by the employer.
About the role
Broadcom is searching for a Physical Verification PD Engineer to join the ASIC Products Division (APD). This position requires in-depth knowledge of Foundry rules, DFM, and experience in silicon tape-out and RTO tapeout for PCIe Switch Products and Enterprise Products in 3nm/2nm nodes.
What you'll do
- Execute chip-level physical verification, DRM runsets for advance nodes, tool flows, and issue resolution. - Manage and guide rules related to top-level floorplan, I/O, and bump planning. - Resolve physical design issues related to chip integration and assembly. - Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC. - Develop best practice guidelines for physical verification flows and runtime optimizations.
What you'll need
- Bachelor’s degree in Electrical Engineering or Electronics Engineering. - 12+ years of relevant experience. - In-depth knowledge of Foundry rules, DFM, and experience in silicon tape-out and RTO tapeout. - Ability to work on-site in person at the San Jose facility.
Nice to have
- Hands-on experience running physical verification (LVS, DRC, ERC, PERC) using EDA tools such as ICV, Calibre, and Pegasus. - Rule deck coding experience in ICV, Calibre, or Pegasus EDA tools. - Experience resolving chip-level DRC/LVS/EMIR issues for advance nodes and tapeout experience. - Experience with Electrical Rule Checking (ERC/PERC) to analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities. - Experience managing automated dummy metal, poly, and diffusion filling strategies for local and global density rules. - Design for Manufacturability (DFM) implementation skills, including critical area analysis (CAA), via-doubling, and edge-displacement rules. - Experience scripting in Python, Tcl, or Perl.
Skills: physical verification, DRC, LVS, Calibre, PERC, DFM
This role has been open 0 days — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 673 |
| Open roles in the wider Physical Implementation family | 41 | 1489 · 109 employers |
| Median days open | 103 d | 64 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical verification, DRC, LVS, Calibre, PERC, DFM
Who's hiring in this category
- Qualcomm · 123 open roles · median 47 d
- AMD · 64 open roles · median 27 d
- Intel Corporation · 40 open roles · median 16 d
- Synopsys · 37 open roles · median 38 d
- NVIDIA · 36 open roles · median 66 d
- Broadcom (this employer) · 34 open roles · median 103 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.