Sr. Staff Physical Design Engineer - Mountain View, CA, United States
$195,000 - $214,000 USD yearly
Originally posted 6 January 2026 by the employer.
Drive 3nm timing closure and physical verification for high-performance ASICs.
About the role
The Sr. Staff Physical Design Engineer implements complex digital blocks from synthesis through physical verification for high-performance ASICs. The role drives timing closure, power integrity, and floorplanning at advanced process nodes (3nm).
What you'll do
- Implement digital blocks in advanced process nodes from synthesis through physical verification using industry standard tools and flows. - Drive full-chip STA signoff, review constraints, debug timing reports, and implement functional and timing ECOs. - Drive power analysis and optimization while balancing area and performance trade-offs. - Drive full-chip floorplanning, IO placement, and clock distribution, including custom clock implementation for functional and test clocks. - Debug and resolve DRC and LVS violations across blocks and top level. - Write TCL, Python, or Shell scripts to automate flows or customize existing design flows.
What you'll need
- Bachelor’s degree in Electrical Engineering or Computer Engineering. - 12+ years of industry experience working as a Physical Design Engineer. - Tape-out experience completing blocks or top-level physical design for large ASICs or mixed-signal chips. - Thorough knowledge of timing closure, LVS, and DRC closure. - Experience with TCL and Python (or other scripting languages).
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering with 8 years of industry experience. - Hands-on experience with Cadence tools. - Tape-out experience with 3nm designs. - Willingness to perform manual layout and learn silicon photonics layout. - EM/IR analysis experience using standard industry signoff tools.
Skills: timing closure, physical verification, advanced process nodes, DRC, LVS
This role has been open 165 days — well above the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 673 |
| Open roles in the wider Physical Implementation family | 7 | 1489 · 109 employers |
| Median days open | 114 d | 64 d (+50 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: timing closure, physical verification, advanced process nodes, DRC, LVS
Who's hiring in this category
- Qualcomm · 123 open roles · median 47 d
- AMD · 64 open roles · median 27 d
- Intel Corporation · 40 open roles · median 16 d
- Synopsys · 37 open roles · median 38 d
- NVIDIA · 36 open roles · median 66 d
- Broadcom · 34 open roles · median 103 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.