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Ayar Labs

Sr. Staff Engineer, Optical Link Design

Ayar Labs San Jose, CA, United States Full-time 5 hours ago
Digital Design & SoC Architecture AI/ML Hardware

$175,000 - $223,000 USD yearly

Focus on link modeling and data analysis for silicon photonics co-packaged optics (CPO) platforms.

About the role

As a member of the Link Design and Architecture team, you will bridge large-scale data analysis and optical link models to optimize the performance of co-packaged optics (CPO) solutions. You will be responsible for ensuring the robustness and performance of silicon photonics optical I/O platforms.

What you'll do

  • Drive link modeling studies to evaluate future product solution spaces and define component-level specifications.
  • Identify key device performance metrics and translate hardware variability into impacts on total link budget and manufacturing yield.
  • Build system-level models based on component-level data and benchmark them against measured system-level data.
  • Work with Photonic and AMS teams to ensure integration across electrical and optical domains.

What you'll need

  • Bachelor's degree in Optics/Photonics, Physics, Electrical Engineering, or a related field.
  • Demonstrated experience in photonics, electrical engineering, high-speed link design, or processing and analyzing large statistical datasets.
  • Understanding of high-speed electrical and/or optical links, as well as optical physics regarding photonic components.
  • Programming proficiency in Python for scientific computing and data analysis.
  • Experience with data analysis libraries including Pandas, NumPy, and SciPy.

Nice to have

  • Master's or Ph.D. in Optics/Photonics, Physics, Electrical Engineering, or a related field.
  • Experience in the design and simulation of PIC components or large-scale integrated optical systems.
  • Experience with laboratory equipment and free-space/fiber optics for optical characterization.
  • Proficiency in behavioral modeling using Verilog-A and knowledge of mixed-signal simulation methodologies.

More semiconductor jobs: Hardware design jobs · San Jose jobs

Market context

This role has been open 150 days — well above the 46-day median for Hardware Systems Engineering roles.

Hardware Systems Engineering · AI ML Hardware

Open roles in category
1126
Median days open
46 d
Category median salary (all employers)
$150k
See the full market breakdown ▾Category comparison, and who else is hiring
How Ayar Labs compares in Hardware Systems Engineering hiring
Metric Ayar Labs All employers we track in this specialty (1126 roles · 109 employers)
Open roles in this specialty 12 1126
Open roles in the wider Software, Firmware & Systems family 24 6531 · 156 employers
Median days open 51 d 46 d (+5 d vs this employer)
Median salary (USD postings) — $150k

Who's hiring in this category

  • Intel Corporation · 88 open roles · median 33 d
  • KLA Corporation · 66 open roles · median 59 d
  • Applied Materials · 60 open roles · median 40 d
  • ASML · 59 open roles · median 17 d
  • NVIDIA · 58 open roles · median 74 d
  • Teradyne · 58 open roles · median 51 d

How we counted: 1126 open Hardware Systems Engineering (AI ML Hardware) roles from 109 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.

Ayar Labs

Ayar Labs

Apply now
San Jose, CA, United States
On-site
Full-time
$175,000 - $223,000 USD yearly
5 hours ago

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