Principal SoC IP & Interconnect Architect
$195,000 - $292,000 USD yearly
About the role
As a Principal SoC IP & Interconnect Architect, you will apply technical expertise and architectural leadership to define and integrate SoC and interconnect IP for Ampere products. You will drive the architecture of high-performance I/O and interconnect subsystems while navigating complex system-level requirements and integration tradeoffs.
What you'll do
- Lead the definition, architecture, and integration of SoC and interconnect IP for Ampere products.
- Own the end-to-end architecture of one or more I/O and interconnect subsystems, balancing performance, scalability, power, reliability, and platform requirements.
- Drive cross-functional alignment with system architects, design, verification, and software teams to deliver cohesive SoC IP solutions.
- Outline subsystem interfaces, integration strategies, and architectural requirements to ensure seamless connectivity across the SoC platform.
- Define subsystem-level SoC architecture in collaboration with CPU and compute-engine teams, aligning with the SoC chassis, global architecture, and integration requirements.
- Influence key technical decisions and resolve architecture and integration tradeoffs throughout the product development lifecycle.
What you'll need
- BS degree in Electrical Engineering, Computer Engineering, or Computer Science with 8+ years of experience, MS degree with 6+ years, or PhD with 3+ years.
- 6+ years of proven SoC architecture or design experience.
- Familiarity with SoC interconnect and coherent fabric architecture.
- Deep understanding of AMBA-based interconnect protocols (AXI and CHI) and their application in high-performance, cache-coherent SoC designs.
- Knowledge of cache-coherent memory systems, DMA traffic, and interconnect performance tradeoffs.
- Hands-on experience developing architectural performance models for bandwidth, latency, scalability, and workload analysis.
- Experience across the full IP lifecycle, from IP selection and integration through silicon validation, performance debug, and bring-up.
Nice to have
- Previous RTL/logic design or design verification experience.
- IP integration experience covering boot/reset flows and performance modeling.
- Background in power delivery, power management, clocking, debug/trace, interrupts, or RAS.
Skills: SoC architecture, interconnect, coherent fabric, AXI, CHI
More semiconductor jobs: SoC design jobs · Santa Clara jobs
This role has been open 80 days — slightly above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 485 |
| Open roles in the wider Digital Design & Verification family | 26 | 3525 · 120 employers |
| Median days open | 24 d | 79 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC architecture, interconnect, coherent fabric, AXI, CHI
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.