Sr. Staff Engineer, Electrical Link Architecture
$190,000 - $223,000 USD yearly
About the role
As a member of the Link Design and Architecture team, you will own the electrical-side modeling that drives the silicon photonics I/O platform, encompassing the analog front end, DSP, and co-simulation models.
What you'll do
- Build and maintain compact models of the analog front end and DSP chain for accurate BER and link-margin prediction.
- Co-design Verilog-A models of the electrical/optical interface, including modulators and photodetectors, with analog/mixed-signal (AMS) designers.
- Reconcile simulation models against silicon measurements in partnership with validation engineers.
- Feed electrical models into link studies, applying standard circuit-design methods such as corners and Monte Carlo to determine specifications and yield.
- Collaborate across AMS, photonics, and validation teams to align modeling with product roadmaps.
- Execute end-to-end link simulations to evaluate device and architecture tradeoffs for current and future designs.
What you'll need
- BS in Electrical Engineering, Physics, or a related field.
- 5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
- Strong working knowledge of analog front-end blocks and DSP architectures that close high-speed links.
- Proficiency in Verilog-A and mixed-signal simulation methodologies.
- Experience with statistical circuit analysis methods, including corners and Monte Carlo.
- Strong Python skills for scientific computing and data analysis.
Nice to have
- Prior industry experience architecting and deploying SerDes into a shipping product.
- MS or Ph.D in Electrical Engineering, Physics, or a related field.
- Hands-on experience with silicon bring-up, validation, or link characterization.
- Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
- Familiarity with Cadence Virtuoso / ADE / Spectre.
- Familiarity with optical transceiver principles, modulation formats, and industry standards.
More semiconductor jobs: Signal integrity jobs · San Jose jobs
This role has been open 51 days — well below the 65-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
256
|
Median days open
65 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (256 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 256 |
| Open roles in the wider Analog & Mixed-Signal family | 8 | 1541 · 115 employers |
| Median days open | 51 d | 65 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Who's hiring in this category
- Synopsys · 39 open roles · median 37 d
- AMD · 22 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 152 d
- NVIDIA · 17 open roles · median 213 d
- Qualcomm · 16 open roles · median 86 d
- Apple · 11 open roles · median 2 d
How we counted: 256 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.