Distinguished Signal Integrity Engineer
$293,000 - $440,000 USD yearly
HFSS, SIWave, and IBIS-AMI channel modeling for high-speed SerDes including PCI-gen5/6/7.
About the role
Our Hardware Design Engineering organization is seeking a Distinguished Signal Integrity Engineer to implement high-performance interconnect solutions for high-bandwidth, connectivity-intensive multi-core processor products, requiring co-design of silicon, package, and PCB.
What you'll do
- Design, simulate, and validate high-performance interconnect solutions across chip, package, and PCB teams to ensure robust signal integrity performance.
- Develop package and PCB layout guidelines along with SI/PI documentation for internal teams and external customers.
- Support product bring-up and direct customer engagements.
- Drive signal integrity analysis methodologies.
- Provide technical leadership in interconnects, advanced packaging, and cross-functional system co-design.
What you'll need
- Bachelor's degree in Electrical or Computer Engineering with 15+ years of related experience, Master's degree with 12+ years, or PhD with 8+ years.
- Expertise in high-speed SerDes serial and parallel interfaces such as PCI-gen5/6/7 or USB/USB-C.
- Transmission line and electromagnetic theory expertise applied to signal integrity and power integrity.
- Hands-on experience creating and simulating 3D models in tools such as HFSS, SIWave, and PowerSI for end-to-end channel modeling and link budget analysis.
- Understanding of behavioral IO models (IBIS, IBIS-AMI) and SerDes TX/RX equalization techniques including CTLE, DFE, and TX equalization.
- Working knowledge of AC/DC power delivery, power integrity analysis, and simultaneous switching noise analysis for memory interfaces.
- Understanding of stack-up manufacturing processes and design limitations considering DFM.
Nice to have
- Experience with both large body-size electronic packages and high-performance PCBs.
Skills: Signal Integrity, Power Integrity, SerDes, HFSS, PCIe, IBIS-AMI
More semiconductor jobs: Signal integrity jobs · Santa Clara jobs
This role has been open 3 days — well below the 65-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
256
|
Median days open
65 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (256 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 256 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1541 · 115 employers |
| Median days open | 8 d | 65 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Skills observed across this category: Signal Integrity, Power Integrity, SerDes, HFSS, PCIe, IBIS-AMI
Who's hiring in this category
- Synopsys · 39 open roles · median 37 d
- AMD · 22 open roles · median 44 d
- Cadence Design Systems · 21 open roles · median 152 d
- NVIDIA · 17 open roles · median 213 d
- Qualcomm · 16 open roles · median 86 d
- Apple · 11 open roles · median 2 d
How we counted: 256 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.