About the role
This role supports the physical layout of analog, mixed-signal, and high-speed integrated circuits, converting schematics into layouts that meet electrical, matching, parasitic, reliability, and manufacturability requirements.
What you'll do
- Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits, including devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.
- Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.
- Run and debug physical verification checks including DRC, LVS, ERC, antenna checks, density checks, and reliability checks.
- Perform parasitic extraction and collaborate with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.
- Support layout floorplanning, block-level integration, top-level chip assembly, and prepare layout databases for tapeout signoff.
- Follow foundry design rules and process-specific layout guidelines to optimize layout for performance, area, power, yield, and reliability.
What you'll need
- Associate degree, bachelor’s degree, or equivalent experience in electrical engineering, microelectronics, or a related field.
- Experience with IC layout tools such as Cadence Virtuoso Layout Suite.
- Good understanding of CMOS device layout and semiconductor process layers.
- Experience running and debugging DRC/LVS using tools such as Calibre, Assura, Pegasus, or similar.
- Ability to read and understand circuit schematics.
- Understanding of parasitic effects, device matching, shielding, and signal integrity.
Nice to have
- Experience with analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I/O.
- Experience with advanced CMOS nodes such as 28 nm, 16 nm, 12 nm, 7 nm, or similar.
- Knowledge of FinFET layout rules and advanced-node restrictions.
- Experience with top-level integration, power routing, ESD planning, and chip finishing.
- Familiarity with electromigration, IR drop, latch-up prevention, and reliability rules.
- Experience with layout automation, SKILL scripting, or Python.
Skills: Cadence Virtuoso, DRC, LVS, Calibre, parasitic extraction, analog layout
More semiconductor jobs: Analog design jobs · Sunnyvale jobs
This role has been open 4 days — well below the 26-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
88
|
Median days open
26 d
|
Category median salary (all employers)
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (88 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 88 |
| Open roles in the wider Analog & Mixed-Signal family | 10 | 1541 · 115 employers |
| Median days open | 4 d | 26 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: Cadence Virtuoso, DRC, LVS, Calibre, parasitic extraction, analog layout
Who's hiring in this category
- Analog Devices · 10 open roles · median 43 d
- NVIDIA · 7 open roles · median 5 d
- onsemi · 7 open roles · median 34 d
- Renesas Electronics · 7 open roles · median 25 d
- Infineon Technologies · 6 open roles · median 22 d
- Marvell Technology · 6 open roles · median 42 d
How we counted: 88 open Analog IC Design (Analog Layout) roles from 30 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.