Sr. Staff Engineer, Electrical Link Architecture
$190,000 - $223,000 USD yearly
Join our Link Design and Architecture team to own the electrical-side modeling that drives our silicon photonics I/O platform.
About the role
This role involves owning the electrical-side modeling that drives the silicon photonics I/O platform, encompassing the analog front end, DSP, and models for circuit and photonics co-simulation end-to-end. The team focuses on the robustness and performance of optical links, from component-level modeling to architecture definition, full link analysis, specification development, and yield prediction.
What you'll do
- Build and maintain compact models of the analog front end and DSP chain for BER and link-margin prediction.
- Co-design Verilog-A models of the electrical/optical interface (modulators, photodetectors) with analog/mixed-signal designers.
- Anchor models to silicon by reconciling simulation against measurement with validation engineers.
- Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
- Collaborate across AMS, photonics, and validation to maintain modeling stack coherence with the product roadmap.
- Run end-to-end link simulations to evaluate device and architecture choices for current product design and future roadmap exploration.
What you'll need
- BS in Electrical Engineering, Physics, or a related field.
- 5+ years of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
- Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
- Proficiency in Verilog-A and mixed-signal simulation methodologies.
- Experience with statistical circuit analysis methods (corners, Monte Carlo).
- Strong Python skills for scientific computing and data analysis.
Nice to have
- Prior industry experience architecting and deploying SerDes into a shipping product.
- MS or Ph.D in Electrical Engineering, Physics, or a related field.
- Hands-on experience with silicon bring-up, validation, or link characterization.
- Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
- Familiarity with Cadence Virtuoso / ADE / Spectre.
- Familiarity with optical transceiver principles, modulation formats, and industry standards.
Skills: electrical-side modeling, analog front end, DSP, high-speed link modeling, SerDes architecture, mixed-signal simulation
This role has been open 97 days — slightly above the 89-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
215
|
Median days open
89 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ayar Labs | Market (215 open roles · 44 companies) |
|---|---|---|
| Open roles in category | 1 | 215 |
| Median days open | 97 d | 89 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: electrical-side modeling, analog front end, DSP, high-speed link modeling, SerDes architecture, mixed-signal simulation
Who's hiring in this category
- AMD · 24 open roles · median 60 d
- Cadence Design Systems · 19 open roles · median 152 d
- Qualcomm · 18 open roles · median 68 d
- Synopsys · 16 open roles · median 52 d
- Broadcom · 11 open roles · median 141 d
- Micron Technology · 9 open roles · median 126 d
Based on 215 open roles at 44 companies in our index. Snapshot 9 Sept 2026.