Sr. Staff Engineer, ASIC Design
$180,000 - $223,000 USD yearly
About the role
The ASIC Sr. Staff Engineer is responsible for the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC.
What you'll do
- Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers.
- Develop and optimize RTL in Verilog for use in complex electro-optical ASICs.
- Develop models and testbenches for digital and mixed-signal blocks.
- Create clear documentation of designs to enable physical implementation, including clocks, timing constraints, floorplan guidance, and testability.
- Bring up, evaluate, and debug in-house custom silicon using Python scripting, firmware, and control systems.
- Contribute to automated design methodologies and flows for ASIC digital design with high-speed interconnects and optical systems.
What you'll need
- BS in Electrical Engineering, Computer Engineering, or related fields.
- 5+ years of work or academic experience in ASIC design.
- Mastery of Verilog and SystemVerilog for both RTL design and verification.
- Proficiency in ASIC verification tools, such as Xcelium, VCS, or Questa.
- Proficiency in low-level programming languages (C, C++) and Python.
- Working knowledge of digital timing constraints, ASIC tool flows, multiple clock domains, and SOC interconnect fabrics (AMBA AXI/AHB/APB).
Nice to have
- MS in Electrical Engineering, Computer Engineering, or related fields.
- Proficiency in ASIC synthesis tools (Genus, Design Compiler) and timing analysis.
- Experience with silicon bring-up, debug, evaluation, and FPGA or microcontroller platforms.
- Working knowledge of custom block integration in digital-top flows (LEF, lib) or the Cadence Virtuoso design environment.
- Experience with DFT methodologies and flows such as scan insertion, BIST, and ATPG.
- Knowledge of high-speed SerDes or SerDes components, optics, and control systems.
Skills: RTL, Verilog, SystemVerilog, ASIC design, electro-optical ASICs, silicon bring-up
More semiconductor jobs: RTL design jobs · San Jose jobs
This role has been open 156 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1096 |
| Open roles in the wider Digital Design & Verification family | 10 | 3525 · 120 employers |
| Median days open | 123 d | 64 d (+59 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: RTL, Verilog, SystemVerilog, ASIC design, electro-optical ASICs, silicon bring-up
Who's hiring in this category
- Qualcomm · 139 open roles · median 73 d
- AMD · 94 open roles · median 50 d
- Synopsys · 90 open roles · median 51 d
- NVIDIA · 47 open roles · median 64 d
- NXP Semiconductors · 45 open roles · median 107 d
- Analog Devices · 41 open roles · median 54 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.