Sr. Staff Design Engineer

Originally posted 30 October 2026 by the employer.

About the role

Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments. Focuses on architecting and developing DDR Memory Controller soft IPs and RISC-V based system design.

What you'll do

• Architect and develop DDR Memory Controller soft IPs, optimizing for latency, size, and frequency.
• Develop complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
• Integrate soft IPs with third-party hardened PHYs and into FPGA software flows.
• Perform static timing analysis (STA), constraint writing, and timing closure.
• Build embedded systems within Lattice FPGAs, including RISC-V based system design, evaluation, and microprocessor implementation.
• Conduct test development, hardware validation, and hardware interoperability testing to validate implementation.

What you'll need

• Bachelor’s degree in Electronics Engineering, Applied Physics, or a related field.
• 8 years of experience as a Design Engineer or in a related field.
• Hands-on experience with FPGA and SoC ASIC development, including FPGA RTL design, logic verification, debug, and timing closure.
• Experience with DDR protocols such as DDR3, DDR4, LPDDR4, or DDR5.
• Background in high-speed interface subsystems and protocols, including PCIe, Ethernet, or MIPI.
• Experience with peripheral IPs including UART, SPI, I2C, and I3C, along with hardware validation and interoperability testing.

Skills: FPGA, RTL, DDR, Memory Controller, STA, RISC-V

More semiconductor jobs: FPGA engineer jobs · San Jose jobs