Sr/ Staff Design Engineer/Architect(Datapath), HBM - Richardson, TX, United States
Originally posted 28 October 2026 by the employer.
Design high-speed datapath circuits across logic-die and core-die architectures for High Bandwidth Memory (HBM).
About the role
This role architects, designs, and optimizes high-speed data paths across logic-die and core-die circuitry for High Bandwidth Memory (HBM) products. You will work on JEDEC and custom HBM solutions, covering read/write datapath designs through silicon bring-up and production.
What you'll do
- Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic. - Develop high-speed, low-latency datapath circuits supporting multi-channel HBM architectures and wide internal buses. - Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes. - Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms. - Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies. - Collaborate with PHY, DFT, verification, layout, and system teams to translate specifications into robust micro-architectures and verify manufacturability.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant industry experience, or a Master’s degree with 4+ years of relevant industry experience. - 2+ years of experience in high-speed digital datapath design (memory, SerDes, or SoC datapath). - 2+ years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.
Nice to have
- Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation. - Working knowledge of layout and floorplanning considerations for high-speed datapath. - Experience with static timing analysis (STA) and timing-closure methodologies. - Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.
Skills: HBM, Datapath, RTL, Schematic, DRAM, Timing Closure
This role has been open 0 days — well below the 70-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
322
|
Median days open
70 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (322 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 170 | 322 |
| Median days open | 81 d | 70 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: HBM, Datapath, RTL, Schematic, DRAM, Timing Closure
Who's hiring in this category
- Micron Technology (this employer) · 170 open roles · median 82 d
- Synopsys · 31 open roles · median 69 d
- Qualcomm · 19 open roles · median 90 d
- SanDisk · 17 open roles · median 56 d
- Broadcom · 16 open roles · median 70 d
- onsemi · 7 open roles · median 101 d
How we counted: 322 open Memory Design (Memory Design) roles from 30 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.