Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging - Austin, Texas, United States
Originally posted 5 September 2026 by the employer — open 17 days.
About the role
This role involves driving SI/PI analysis and optimization of advanced packaging solutions for machine learning and data center ASICs. You will own the package-level signal and power integrity strategy from early architecture trade-offs through design closure, measurement, and validation.
What you'll do
- Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
- Design and optimize package stack-ups, including dielectric material selection, impedance control, layer assignment, and RDL routing.
- Perform high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces.
- Analyze and optimize the package PDN end-to-end, including decoupling strategy, plane resonance, IR drop, and AC impedance.
- Characterize and model on-die capacitance, deep trench capacitors (DTCs), and integrated passive device (IPD) capacitors.
- Perform 3D/2.5D EMIR analysis using tools such as Ansys RedHawk-SC 3DIC, Cadence Voltus, or equivalent.
What you'll need
- Experience with package-level SI/PI analysis.
- Experience with 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
- Proficiency in high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams).
- Knowledge of PDN analysis for decoupling strategy, plane resonance, IR drop, and AC impedance.
- Familiarity with on-die capacitance, deep trench capacitors (DTCs), and integrated passive device (IPD) capacitors.
- Experience with 3D/2.5D EMIR analysis using tools like Ansys RedHawk-SC 3DIC or Cadence Voltus.
Skills: package-level SI/PI, 2.5D, 3D-IC, fan-out, silicon interposer, high-speed channel simulations
This role has been open 17 days — well below the 84-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
84 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (39 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 39 |
| Median days open | 17 d | 84 d (−67 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: package-level SI/PI, 2.5D, 3D-IC, fan-out, silicon interposer, high-speed channel simulations
Who's hiring in this category
- Qualcomm · 5 open roles · median 84 d
- Marvell Technology · 4 open roles · median 75 d
- Micron Technology · 4 open roles · median 131 d
- NVIDIA · 4 open roles · median 43 d
- AMD · 3 open roles · median 46 d
- Applied Materials · 2 open roles · median 72 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 20 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.