Sr. Principal SoC Power Management Architect
$225,500 - $338,500 USD yearly
About the role
As a Sr. Principal SoC Power Management Architect, you will be responsible for driving SoC-level power management architecture, translating business power and performance requirements into SoC and IP-level specifications. You will collaborate with SoC global and IP teams to meet product power, performance, and energy efficiency targets.
What you'll do
- Own end-to-end power management architecture, translating business power and performance goals into actionable SoC and IP requirements.
- Drive SoC and subsystem power management architecture while partnering with subsystem architects to define new features and expand IP power capabilities using data-driven analysis.
- Evaluate hardware, software, and firmware trade-offs to deliver verifiable power management solutions.
- Enable HW-SW codesign execution by partnering with senior architects and firmware developers to ensure implementation matches architectural intent.
- Lead architectural reviews and provide technical direction to pre- and post-silicon verification teams for architecture definitions, documentation, and silicon delivery.
What you'll need
- 8+ years of hands-on power architecture and SoC low-power expertise, including DVFS/power-state control, power-state residency, and performance-per-watt trade-offs.
- Deep hardware development experience from specification to integration of low-power features, with familiarity in RTL-level design and verification constraints.
- Proven power optimization expertise using measured results to improve SoC/IP power-saving effectiveness and validate net impact on performance and energy.
- Expert knowledge of SoC low-power modes and IP low-power capabilities, covering power modes/states, wake-up/latency, and retention behavior.
- Experience with the ownership of SoC-level low-power management flows, orchestrating subsystem entry/exit and power sequencing across corner cases and workloads.
- BS in Electrical Engineering, Computer Engineering, or Computer Science with 12 years of experience, MS with 8 years, or PhD with 5 years.
Nice to have
- Familiarity with SW/FW and microcontrollers.
- Experience with HW/SW Co-Design.
- Knowledge of ARM Architecture.
- Expertise in power states.
Skills: SoC power management architecture, DVFS/power-state control, HW development, RTL-level design, power optimization
More semiconductor jobs: SoC design jobs · Santa Clara jobs
This role has been open 93 days — well above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ampere Computing | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 485 |
| Open roles in the wider Digital Design & Verification family | 26 | 3525 · 120 employers |
| Median days open | 24 d | 79 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC power management architecture, DVFS/power-state control, HW development, RTL-level design, power optimization
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.