Sr Principal Signal Integrity Engineer - Beaverton, OR, United States
$115,800 - $151,935 USD yearly
Originally posted 16 June 2026 by the employer — open 86 days.
About the role
This role involves improving signal and power integrity performance, completing production design analysis, and characterizing and measuring high-speed interconnects. You will be part of a technical group working with customers and engineers across multiple sites, focusing on probe cards and load boards.
What you'll do
- Perform signal and power integrity analysis for high-speed interconnects (PCB, package, MLO, probe card).
- Develop and validate electrical models for Transmission lines, vias, connectors, and Power Distribution Network (PDN) structures.
- Use EM and circuit tools (e.g., HFSS, ADS, SIwave, PowerSI) for Frequency-domain and time-domain analysis.
- Define and execute SI validation plans using VNA, TDR, TDT, and high-speed measurement setups.
- Drive simulation-to-measurement correlation and root cause analysis.
- Provide design guidelines, constraints, and best practices to layout teams and electrical design engineers.
What you'll need
- 8+ years of relevant experience in SI/PI analysis and design.
- Strong understanding of Transmission line theory.
- Strong understanding of Power integrity principles.
- Experience with tools such as HFSS, ADS, SIwave, PowerSI, PowerDC, SPICE, Allegro, MATLAB.
- Hands-on experience with measurement tools (VNA, TDR/TDT).
- Experience with high-speed interfaces (PAM4, SerDes, PCIe, HBM).
Nice to have
- Scripting/automation (Python, MATLAB).
- Experience in advanced packaging, probe cards, or fine-pitch interconnects.
Skills: signal integrity, power integrity, SerDes, HFSS, VNA, TDR
This role has been open 100 days — slightly above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | FormFactor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 8 | 1317 · 100 employers |
| Median days open | 89 d | 91 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: signal integrity, power integrity, SerDes, HFSS, VNA, TDR
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.