$135,900 - $295,000 USD yearly
About the role
Skyworks Power Management division is seeking a Top-level Design Verification Engineer to support power management solutions for mobile, consumer, IoT, and industrial applications. The position focuses on power loss protection, PMICs, motor control, and battery management IC solutions.
What you'll do
- Serve as customer-facing verification engineer for catalog and custom power-management ICs, including motor driver, power-loss protection, point of load, and battery management IC solutions.
- Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a focus on customer use-cases.
- Develop constrained random tests and automated checkers within the top-level design verification (TLDV) UVM environment.
- Build high-performance, accurate RNM or VerilogAMS models to support top-level simulation.
- Collaborate with the design team to resolve issues identified during verification and partner with internal test teams to ensure device first-pass testability.
- Continuously improve and align verification methodologies with industry practices, automating verification tasks where applicable.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field, with a focus on mixed-signal circuit design and verification.
- 15+ years of experience (or equivalent advanced education and experience) in AMS design or verification of analog and power-management ICs.
- Proficiency in UVM environments, including test cases, coverage models, and global checkers.
- In-depth knowledge of power-management building blocks such as LDO, Amplifiers, Bandgaps, DCDC regulators, Oscillators, and asynchronous state machines.
- Expertise in mixed-signal concepts including Spice/Spectre and event-based simulators, co-simulation environments, simulation debug, and silicon debug.
- Willingness to travel up to 10% of the time.
Nice to have
- Master’s degree in Electrical Engineering or a related field, with a focus on mixed-signal circuit design and verification.
- Experience in top-down design methodology.
- Proficiency in shell or Python scripting.
- Familiarity with SV-UDN/EENET modeling techniques.
- Experience with both GUI and command-line simulation flows.
- Proficiency with SystemVerilog Assertions and functional coverage.
- Understanding of integrating AI into a verification workflow.
Skills: UVM, AMS, power-management ICs, RNM, VerilogAMS
More semiconductor jobs: Verification engineer jobs
This role has been open 11 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Skyworks | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1345 |
| Open roles in the wider Digital Design & Verification family | 14 | 3525 · 120 employers |
| Median days open | 137 d | 58 d (+79 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, AMS, power-management ICs, RNM, VerilogAMS
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.