Sr. Principal Engineer, SoC Architect
$250,000 - $304,000 USD yearly
About the role
The Senior Principal Engineer, SoC Architect defines and drives SoC architectures for high-performance semiconductor products across compute, memory, interconnect, security, and peripheral subsystems. The role focuses on high-speed interfaces, subsystem partitioning, architectural modeling, and power/performance optimization from concept through silicon realization.
What you'll do
- Define end-to-end SoC architecture, subsystem partitioning, and top-level integration strategies across compute, memory, interconnect, security, and peripheral subsystems.
- Drive architectural tradeoff analysis balancing performance, power, area (PPA), latency, scalability, and cost.
- Lead the architecture and integration of high-speed interfaces, including PCIe, Ethernet, USB, SerDes, CXL/UCIe, and advanced interconnect protocols.
- Develop architectural models, traffic analysis frameworks, and workload characterization for system-level performance modeling and dynamic performance management.
- Provide architectural leadership and technical reviews across multiple SoC programs while collaborating with RTL, verification, firmware, software, and validation teams.
What you'll need
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of experience in SoC/system architecture and semiconductor product development.
- Proven expertise in large-scale SoC architecture definition and subsystem integration.
- Strong understanding of high-speed I/O architectures, on-chip interconnects, coherency fabrics, memory subsystem architecture, and power/performance optimization techniques.
- Experience with architecture modeling tools, simulation environments, and performance analysis methodologies.
Nice to have
- Deep expertise in high-speed I/O technologies such as PCIe Gen5/Gen6, CXL, UCIe, HBM, or advanced SerDes architectures.
- Experience with heterogeneous compute architectures involving CPU, GPU, AI/ML accelerators, or DSP subsystems.
- Knowledge of chiplet-based architectures and advanced packaging technologies.
- Experience with silicon bring-up, post-silicon debug, and system validation.
- Familiarity with automotive, AI/ML, datacenter, networking, or mobile SoC platforms.
- Publications, patents, or industry contributions in SoC or high-speed interconnect architecture.
Skills: SoC architecture, high-speed I/O, PCIe, CXL/UCIe, performance modeling
More semiconductor jobs: SoC design jobs · San Jose jobs
This role has been open 156 days — well above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
485
|
Median days open
79 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (485 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 485 |
| Open roles in the wider Digital Design & Verification family | 10 | 3525 · 120 employers |
| Median days open | 137 d | 79 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC architecture, high-speed I/O, PCIe, CXL/UCIe, performance modeling
Who's hiring in this category
- Qualcomm · 78 open roles · median 88 d
- NVIDIA · 67 open roles · median 81 d
- AMD · 39 open roles · median 68 d
- Arm Holdings · 29 open roles · median 11 d
- Apple · 28 open roles · median 12 d
- Micron Technology · 20 open roles · median 111 d
How we counted: 485 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.