Sr Principal Application Engineer
$143,500 - $266,500 USD yearly
Originally posted 9 July 2026 by the employer. Relisted by the employer on 6 November 2026.
About the role
Cadence is seeking a Sr Principal Application Engineer to provide hands-on technical support to customers in backend digital design implementation and signoff from RTL to GDSII. The role focuses on synthesis, place and route, design closure, and timing/power signoff on advanced technology nodes down to sub-5nm.
What you'll do
- Lead technical campaigns and customer engagements focused on RTL to GDSII digital implementation, design closure, and timing/power signoff.
- Support execution on critical customer tapeouts, driving tool optimization to improve power, performance, and area (PPA).
- Collaborate directly with R&D teams to improve EDA tools and methodologies based on customer flow requirements.
- Deliver technical presentations, lead customer discussions, and guide technical implementation strategies.
- Amend and extend design implementation flows using Tcl, Perl, or Python scripting to resolve issues and streamline results.
What you'll need
- MS degree in Computer Science, Electrical Engineering, Computer Engineering, or related field with 10+ years of industry experience.
- Deep knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
- Experience with IC digital implementation flows and backend EDA tools for synthesis, place and route, IR drop, and timing/power closure from RTL to GDSII.
- Direct experience in floorplanning, power planning, and low-power techniques for System-on-Chip (SoC) designs.
- Scripting expertise in Perl, Tcl, or Python for flow automation and process improvement.
- Experience with advanced technology nodes, including sub-5nm and below.
Nice to have
- Prior experience with the Cadence tool suite, including Genus, Innovus, Conformal, Tempus, Modus, or Voltus.
- Experience with front-end EDA flows including DFT and Logical Equivalence Checking.
- Hands-on implementation of advanced clock tree synthesis techniques such as SoC clock distribution, clock mesh, and H-Tree.
- Practical experience with multi-corner design closure across timing, DRC, LVS, and EMIR.
Skills: backend digital design, RTL to GDSII, synthesis, place and route, design closure
More semiconductor jobs: Cadence Design Systems jobs · EDA tools engineer jobs
This role has been open 120 days — well above the 66-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
732
|
Median days open
66 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (732 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 162 | 732 |
| Open roles in the wider Physical Implementation family | 196 | 1615 · 117 employers |
| Median days open | 161 d | 66 d (+95 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: backend digital design, RTL to GDSII, synthesis, place and route, design closure
Who's hiring in this category
- Cadence Design Systems (this employer) · 160 open roles · median 161 d
- Synopsys · 60 open roles · median 56 d
- Micron Technology · 49 open roles · median 43 d
- NVIDIA · 44 open roles · median 101 d
- Renesas Electronics · 40 open roles · median 14 d
- Qualcomm · 34 open roles · median 87 d
How we counted: 732 open EDA/CAD Engineering (EDA Tools) roles from 78 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.