Physical Design & EDA
About the role
AMD is hiring an MTS Mask Design Engineer to research, design, develop, and test electronic components and systems for semiconductor manufacturing. You will oversee mask designs for complex macros and tiles integrated at the SOC level.
What you'll do
- Oversee mask designs for complex macros and tiles to be integrated at the SOC level.
- Verify mask designs against physical and electrical checks and guidelines.
- Execute DRC/LVS debug, address EM/IR and density concerns, and contribute across the design flow.
- Exercise independent judgment to select methods, techniques, and evaluation criteria for projects of technical importance.
- Apply engineering principles, best practices, and technologies to the design, development, and testing of company proprietary products.
What you'll need
- Master’s degree in Electrical Engineering, Electronics Engineering, or a related field plus 3 years of engineering experience (or Bachelor’s degree plus 5 years of progressive post-baccalaureate experience).
- 3 years of experience in IC Mask Layout Design and Cadence Design environment.
- 3 years of experience with Analog and RF/High-Speed design.
- 3 years of experience with Virtuoso XL/EXL/MXL and Calibre verification tools.
- 3 years of experience performing layout vs. schematic (LVS) and design rule checks (DRC).
- 3 years of experience with advanced layout techniques at nodes 16nm and below, top-level and block-level floorplanning, and isolation techniques.
- 3 years of experience with Design Rules, minimization of parasitic effects, and IR drop.
Skills: IC Mask Layout Design, Virtuoso, Calibre, LVS, DRC, floorplanning
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