Sr. Principal Analog Mixed-Signal Design Engineer - Shinagawa, Tokyo, Japan

Originally posted 26 December 2025 by the employer — open 257 days.

About the role

This role involves building precision timing circuits, leveraging SiTime's MEMS technology. These products have applications ranging from high-performance Networking and Communications Infrastructure to ultra-low power Mobile platforms, including wearable devices.

What you'll do

• Contribute to the architectural definition of the design and chip integration.
• Lead chip level design and verification simulations to ensure building blocks meet specifications.
• Work with Layout Engineers to validate proper layout using best-known methods.
• Document assigned blocks and conduct preliminary and final design review meetings.
• Participate in chip bring-up, evaluation, and characterization, focusing on owned blocks.
• Coach, mentor, and develop junior/mid-level analog designers.

What you'll need

• M.S. in Electrical Engineering or related field with minimum 15 years of experience, or Ph.D. in Electrical Engineering with minimum 12 years of experience.
• Excellent academic record with published research projects prototyped and proven in silicon.
• Detailed knowledge of CMOS circuits and noise analysis.
• Core expertise in one of the following: Integer-N and fractional-N PLL, Sigma-Delta ADCs, Temperature sensor, Analog and digital filters, Quartz or MEMS oscillator, Sub-threshold circuits, Low noise regulator and bandgap, High-speed output drivers.
• Ability to oversee circuit layout for critical blocks.
• Knowledge of programming languages: MATLAB, VerilogA.
• Proficient in using Cadence analog design tools.

Nice to have

• Excellent written and verbal communication skills.
• Ability to work well with others in a collaborative team environment.

Skills: Analog Mixed-Signal, architectural definition, chip level design, PLL, Sigma-Delta ADCs