Sr Physical Design Engineer - CA, Santa Clara, United States
Originally posted 23 October 2026 by the employer.
Focus on multi-gigabit SerDes PHY and advanced IP RTL-to-GDS implementation.
About the role
Contribute across the full RTL-to-GDS implementation lifecycle, working on timing, power, area, and physical quality targets. The role focuses on high-performance, multi-gigabit SerDes PHY and advanced IP designs.
What you'll do
- Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff. - Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities. - Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets. - Perform and support logic equivalence, timing, physical, and electrical quality checks. - Support floorplanning, design methodology development, IP integration, and final signoff of large, high-performance IP blocks. - Troubleshoot implementation and timing challenges in collaboration with design teams to drive issues to closure.
What you'll need
- Experience taking digital designs through the RTL-to-GDS physical design flow. - Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic. - Experience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization. - Knowledge of timing, power, and area optimization techniques, plus understanding of digital circuit techniques and logic optimization for high-speed, low-power applications. - Experience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks. - Bachelor's or master’s degree in Electrical Engineering, Computer Science, or a related technical discipline, or equivalent practical experience in semiconductor or physical design engineering.
Nice to have
- Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs. - Verilog experience. - Familiarity with schematic, layout, circuit simulation, or logic simulation tools. - Experience developing, automating, or improving physical design methodologies and flows.
Skills: RTL-to-GDS, place and route, synthesis, STA, SerDes PHY
This role has been open 0 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
673
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (673 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 64 | 673 |
| Open roles in the wider Physical Implementation family | 91 | 1494 · 109 employers |
| Median days open | 26 d | 63 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL-to-GDS, place and route, synthesis, STA, SerDes PHY
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD (this employer) · 63 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 68 d
- Synopsys · 37 open roles · median 37 d
- Broadcom · 34 open roles · median 102 d
How we counted: 673 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.