RET Recipe Engineer (R&D) - Dallas, TX, United States
Originally posted 22 October 2026 by the employer.
About the role
As a Resolution Enhancement Techniques (RET) Technologist, you will define, design, model, implement, and document analog, digital, and RF integrated circuits. The role focuses on RET and lithography requirements across 45 nm, 28 nm, 22 nm, or 20 nm technology nodes.
What you'll do
- Work with designers and fab engineers to understand lithography requirements for RET. - Translate lithography requirements into an implementation plan for RET-recipe code. - Write and review RET-recipe code. - Create test cases for RET-recipe code. - Review large RET-output layouts for quality.
What you'll need
- Master’s degree in Electrical Engineering, Physics, Computer Science, Chemistry, or a related field. - 5+ years of experience in semiconductor photolithography or RET development. - Lithography and RET expertise for the 45 nm, 28 nm, 22 nm, or 20 nm technology nodes. - Expertise in writing, debugging, and validating RET recipes. - Programming experience in either a Linux or Unix environment. - Strong knowledge of advanced lithography processes, lithography simulation techniques, mask making, and RET techniques used in semiconductor manufacturing and process development.
Nice to have
- Familiarity with physical layout (OASIS, GDSII): viewing, measuring, and manipulating it. - Experience with code-version control, such as Git. - Experience with software testing and Quality Assurance (QA). - Experience with coding in Python. - Experience with writing test plans. - Experience with coding in Tcl.
Skills: RET, photolithography, recipe code, OPC, lithography simulation
This role has been open 0 days — well below the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (683 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 683 |
| Open roles in the wider Physical Implementation family | 17 | 1489 · 110 employers |
| Median days open | 168 d | 72 d (+96 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: RET, photolithography, recipe code, OPC, lithography simulation
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 149 d
- Synopsys · 62 open roles · median 40 d
- Micron Technology · 46 open roles · median 49 d
- Qualcomm · 37 open roles · median 73 d
- GlobalFoundries · 36 open roles · median 28 d
- Keysight Technologies · 34 open roles · median 76 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.