Sr. Packaging Engineer (TERADYNE, North Reading, MA)
$175,300 - $280,600 USD yearly
Originally posted 15 September 2026 by the employer — open 3 days.
About the role
This role supports advanced measurement ASIC products within the Semiconductor Test Division.
What you'll do
- Lead ASIC package signal and power integrity architecture, including stackup strategy, bump and BGA escape planning, and package-to-board co-design.
- Develop package and PCB layout constraints for high-speed serial links, clocks, DUT IO, power rails, and sensitive analog or mixed-signal interfaces.
- Collaborate with ASIC design, PCB design, mechanical, thermal, test, characterization, manufacturing, procurement, quality, and external suppliers.
- Build and review time-domain and frequency-domain models for interconnect structures.
- Support package-level power distribution network planning and review activities.
- Partner with substrate, package, PCB fabrication, assembly, and EDA tool suppliers to evaluate design rules.
What you'll need
- Master’s degree in Electrical Engineering, Packaging Engineering, or a closely related technical discipline, or equivalent experience.
- Extensive industry experience in semiconductor package design, package and board interconnect modeling, signal integrity, power integrity, or high-speed mixed-signal hardware development.
- Experience leading SI/PI design and signoff for complex package, board, and system-level interconnects.
- Strong knowledge of electromagnetic field theory, transmission-line theory, frequency-domain network analysis, high-speed digital signaling, analog/RF design considerations, package-to-board co-design, and power-distribution-network design.
- Experience with substrate stackup definition, via and escape design, return-path management, differential and single-ended routing, power and ground assignment, bump or BGA mapping, package construction documentation, and supplier DFM rule review.
- Experience with 2D and 3D electromagnetic field solvers and package or board extraction methods.
- Hands-on experience using Vector Network Analyzers, TDR/TDT, high-speed oscilloscopes, probes, fixtures, and coupon structures.
- Ability to create package and PCB constraints, signoff criteria, simulation plans, correlation plans, and design-review evidence.
Nice to have
- PhD or equivalent advanced technical experience.
- Cadence Sigrity, Clarity, Allegro/APD, Integrity/System Planner, Celsius, Allegro X/Aurora, and related Cadence tool flows.
- Programming or automation experience with Python, Tcl, MATLAB, Perl, C/C++, C#, Visual Basic or similar tools for data processing, S-parameter handling, simulation automation, test automation, or design-flow efficiency.
Skills: package design, signal integrity, power integrity, high-speed mixed-signal, package-to-board co-design
This role has been open 0 days — well below the 64-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
196
|
Median days open
64 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (196 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 196 |
| Open roles in the wider Process, Fab & Equipment family | 115 | 9374 · 108 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: package design, signal integrity, power integrity, high-speed mixed-signal, package-to-board co-design
Who's hiring in this category
- Infineon Technologies · 28 open roles · median 29 d
- Micron Technology · 19 open roles · median 140 d
- Renesas Electronics · 19 open roles · median 22 d
- Intel Corporation · 12 open roles · median 146 d
- Monolithic Power Systems · 12 open roles · median 182 d
- onsemi · 7 open roles · median 62 d
How we counted: 196 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.