Sr. Packaging Engineer (Semiconductor) - IND - Hyderabad, India
Originally posted 1 October 2026 by the employer.
This role focuses on advanced package architectures (WLCSP, DFN, QFN, flip-chip, multi-die) for TVS, TDS, and Hot Switch protection products.
About the role
This role involves leading the definition, development, and qualification of advanced package architectures for semiconductor products. The focus includes ensuring electrical, thermal, and mechanical performance requirements are met for TVS, TDS, and Hot Switch protection products.
What you'll do
- Lead advanced package development and qualification for semiconductor products.
- Serve as a technical interface with external assembly and test (OSAT) partners.
- Support reliability qualification plans in accordance with JEDEC and AEC-Q101 standards.
- Perform systematic failure analysis of package-related defects and implement corrective actions.
- Conduct package-level electrical and thermal simulations to optimize performance.
- Contribute technical input to the advanced packaging technology roadmap.
What you'll need
- Bachelor's degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a closely related field.
- Minimum of 5 years of progressive experience in semiconductor packaging engineering.
- Hands-on experience with WLCSP, DFN, QFN, SOD, SOT, and flip-chip assemblies.
- Direct experience working with OSAT partners in a technical capacity.
- Proven experience executing JEDEC and AEC-Q101 reliability qualification programs.
- Deep understanding of semiconductor assembly processes including wafer dicing, die attach, wire bonding, molding, plating, and wafer-level packaging processes such as WBC and CDAF.
- Proficiency in failure analysis techniques including cross-sectioning, SEM/EDX, SAT, and optical microscopy.
- Working knowledge of package-level electrical and thermal simulation tools.
- Familiarity with statistical process control (SPC), CPK analysis, and DOE methodologies.
- Understanding of ESD, TVS, and protection IC device physics and package parasitics.
Nice to have
- Master's degree or PhD.
Skills: semiconductor packaging, OSAT, reliability qualification, failure analysis, assembly processes
This role has been open 26 days — well below the 58-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
214
|
Median days open
58 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Semtech | All employers we track in this specialty (214 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 214 |
| Open roles in the wider Process, Fab & Equipment family | 22 | 10125 · 107 employers |
| Median days open | 26 d | 58 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: semiconductor packaging, OSAT, reliability qualification, failure analysis, assembly processes
Who's hiring in this category
- Renesas Electronics · 30 open roles · median 39 d
- Infineon Technologies · 25 open roles · median 43 d
- Micron Technology · 21 open roles · median 42 d
- onsemi · 17 open roles · median 32 d
- Intel Corporation · 11 open roles · median 111 d
- Monolithic Power Systems · 11 open roles · median 221 d
How we counted: 214 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.