$135,900 - $295,000 USD yearly
Lead mixed-signal design verification for power-loss protection, PMICs, and motor control ICs using UVM and RNM/VerilogAMS modeling.
About the role
Skyworks is seeking a Sr. Mixed Signal Design Verification Manager to lead top-level design verification efforts within the Power Management division. The team develops power-loss protection, PMICs, motor control, and battery management solutions across mobile, consumer, IoT, and industrial applications.
What you'll do
- Manage and grow a verification engineering team ranging from entry level to senior principal level.
- Drive technical strategy and metric-driven verification plans based on IC functional, performance, and test specifications.
- Develop constrained random tests and automated checkers within a top-level design verification (TLDV) UVM environment.
- Build RNM or VerilogAMS models to support top-level mixed-signal simulation.
- Serve as customer-facing technical verification contact for catalog and custom power-management ICs.
- Partner with internal design and test teams to resolve simulation defects and ensure first-pass silicon testability.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field with a focus on mixed-signal circuit design and verification.
- 15+ years of experience (or equivalent advanced education and experience) in AMS design or verification of analog and power-management ICs.
- Experience managing or serving as a functional team lead.
- Hands-on experience with UVM, analog and digital design fundamentals, and system-level power-management IC architectures.
- Technical expertise in mixed-signal concepts including Spice/Spectre, event-based simulators, co-simulation environments, and silicon debug.
- Willingness to travel up to 10% of the time.
Nice to have
- Master’s degree in Electrical Engineering or a related field.
- Experience in top-down design methodology.
- Proficiency in shell or Python scripting.
- Familiarity with SV-UDN/EENET modeling techniques.
- Proficiency with SystemVerilog Assertions and functional coverage.
- Understanding of integrating AI into a verification workflow.
Skills: UVM, AMS, VerilogAMS, RNM, power-management ICs
More semiconductor jobs: Verification engineer jobs
This role has been open 11 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1345
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Skyworks | All employers we track in this specialty (1345 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1345 |
| Open roles in the wider Digital Design & Verification family | 14 | 3525 · 120 employers |
| Median days open | 137 d | 58 d (+79 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, AMS, VerilogAMS, RNM, power-management ICs
Who's hiring in this category
- Qualcomm · 117 open roles · median 52 d
- Apple · 113 open roles · median 11 d
- NVIDIA · 105 open roles · median 72 d
- AMD · 85 open roles · median 68 d
- Synopsys · 74 open roles · median 52 d
- SiFive · 57 open roles · median 66 d
How we counted: 1345 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.