Sr. Member Technical Staff - ESD and Latch-Up - HBM - Folsom, CA, United States
$177,000 - $334,000 USD yearly
Originally posted 5 August 2026 by the employer.
Define ESD and latch-up architecture across base die, DRAM stacks, and TSV interfaces for HBM products.
About the role
Define ESD and latch-up architecture for HBM products across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation across advanced nodes and 3D integration.
What you'll do
- Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects.
- Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging.
- Establish ESD/LUP standards, rule decks, and signoff criteria.
- Drive correlation between design assumptions, silicon validation, and field reliability.
- Partner with foundry and packaging teams on system-level ESD challenges.
What you'll need
- MS or PhD in Electrical Engineering or related field, or equivalent practical experience.
- 10+ years of experience in ESD and latch-up design and reliability.
- Expertise in advanced CMOS technologies such as FinFET or GAA.
- Experience with 3D IC, TSV, or die-to-die interfaces.
Nice to have
- Experience defining architecture across multi-die or stacked memory systems.
- Background in ESD device or circuit design.
- Experience developing PDK collateral or ESD rule decks.
- Experience debugging silicon failures related to ESD or latch-up.
- Demonstrated technical leadership across cross-functional teams.
This role has been open 129 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
70 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (696 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 696 |
| Open roles in the wider Physical Implementation family | 77 | 1494 · 109 employers |
| Median days open | 51 d | 70 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 150 d
- Synopsys · 63 open roles · median 41 d
- Micron Technology (this employer) · 46 open roles · median 50 d
- GlobalFoundries · 38 open roles · median 24 d
- Qualcomm · 37 open roles · median 74 d
- Keysight Technologies · 34 open roles · median 77 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.