Sr. Manager, Physical Design Engineering, Annapurna Labs - Austin, Texas, United States
Originally posted 22 September 2026 by the employer — open 0 days.
Annapurna Labs designs custom silicon powering AWS’s cloud infrastructure, including Inferentia and Trainium Systems.
About the role
This role involves leading a Physical Design team to deliver multi-billion-transistor ML accelerator SoCs on latest tech nodes.
What you'll do
- Build, hire, and develop a physical design team of 10-15 engineers.
- Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products.
- Institutionalize continuous PPA improvement through benchmarking frameworks, regression tracking, and design-quality dashboards.
- Provide hands-on technical leadership on multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
- Lead technology node enablement for 2nm and beyond, including PDK evaluation, reference flow development, and PPA pathfinding.
- Define and deploy innovative RTL2GDS methodologies and CAD flows, optimizing cloud infrastructure for PD compute.
- Own tapeout execution, including readiness reviews, foundry submittal, and mask data coordination.
What you'll need
- Experience building, hiring, and developing a physical design team.
- Expertise in PPA target-setting and hierarchical methodology.
- Background in timing closure and PDN architecture.
- Knowledge of 2.5D / 3D cross-die integration.
- Experience with RTL2GDS methodologies and CAD flows.
- Understanding of foundry partners and EDA vendors.
Skills: physical design team, PPA target-setting, timing closure, 2.5D / 3D cross-die integration, RTL2GDS methodologies
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
606
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (606 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 606 |
| Open roles in the wider Physical Implementation family | 7 | 1407 · 108 employers |
| Median days open | 28 d | 61 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design team, PPA target-setting, timing closure, 2.5D / 3D cross-die integration, RTL2GDS methodologies
Who's hiring in this category
- Qualcomm · 111 open roles · median 43 d
- Broadcom · 38 open roles · median 71 d
- NVIDIA · 38 open roles · median 46 d
- AMD · 35 open roles · median 41 d
- Synopsys · 27 open roles · median 60 d
- Renesas Electronics · 25 open roles · median 48 d
How we counted: 606 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.