Sr IC Layout Engineer - Hanoi, VN, Vietnam
Originally posted 28 August 2026 by the employer.
About the role
This role involves preparing IC layouts for tapeout, performing schematic entry, IC layout, and verification for RFICs.
What you'll do
- Collaborate with design engineers to prepare IC layouts for tapeout on SiGe, CMOS, SOI, GaAs, and GaN technologies.
- Perform Cell and Chip level schematic entry, IC layout, and verification (LVS, DRC, ERC) for RFICs.
- Floorplan, chip layout, routing, and verification, and support/assist in tapeout.
- Develop documentation and training materials.
What you'll need
- Bachelor of Science Degree, or equivalent experience.
- 5+ years of work experience.
- Proficiency with CAD tools such as Cadence Virtuoso, Mentor Graphics Calibre, AWR, and Keysight ADS.
- Experience with Linux and Windows computer systems.
Nice to have
- Experience with Linux shell scripts.
- Experience with Skill.
- Experience with AMPLE.
- Experience with Perl.
- Experience with Python.
Skills: IC layouts, SiGe, CMOS, SOI, GaAs, GaN, RFICs, Cell and Chip level schematic entry, LVS, DRC, ERC, Cadence Virtuoso
This role has been open 31 days — slightly above the 24-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
45
|
Median days open
24 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | QORVO | All employers we track in this specialty (45 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 45 |
| Open roles in the wider Analog & Mixed-Signal family | 70 | 1364 · 107 employers |
| Median days open | 31 d | 24 d (+7 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: IC layouts, SiGe, CMOS, SOI, GaAs, GaN, RFICs, Cell and Chip level schematic entry, LVS, DRC, ERC, Cadence Virtuoso
Who's hiring in this category
- Celero · 8 open roles · median 30 d
- Analog Devices · 6 open roles · median 10 d
- Broadcom · 3 open roles · median 6 d
- Marvell Technology · 3 open roles · median 23 d
- onsemi · 3 open roles · median 33 d
- QORVO (this employer) · 3 open roles · median 31 d
How we counted: 45 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.