Sr. Fellow -- Memory PHY Architect - CA, Santa Clara, United States
$209,000 - $230,000 USD yearly
Originally posted 26 December 2025 by the employer — open 257 days.
This role focuses on Memory PHY solutions in advanced CMOS technologies, including DDR, LPDDR, GDDR, and HBM.
About the role
The focus is on setting technical direction, guiding critical design decisions, and enabling teams to deliver differentiated mixed-signal IP across future SoCs.
What you'll do
- Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.
- Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.
- Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations.
- Support post-silicon bring-up, validation, characterization, optimization, and product readiness.
- Mentor and advise engineers and architects.
What you'll need
- 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design.
- Deep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations.
- Strong understanding of advanced CMOS technologies and modern design methodologies.
Nice to have
- Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes.
- Experience owning or shaping architecture across multiple successful tape-outs.
- Advanced degree in Electrical Engineering or related field.
Skills: Memory PHY, DDR, LPDDR, GDDR, HBM, high-speed I/O circuit
This role has been open 171 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 24 | 217 |
| Median days open | 61 d | 91 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Memory PHY, DDR, LPDDR, GDDR, HBM, high-speed I/O circuit
Who's hiring in this category
- AMD (this employer) · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.