Sr. Engineer, Silicon Validation
$160,000 - $192,000 USD yearly
Validate optical chiplets across SerDes, photonic, and mixed-signal blocks.
About the role
You will own the silicon bringup and validation of optical chiplets. You will execute post-silicon bringup and characterization across SerDes, photonic, and mixed-signal blocks, building test infrastructure and automation.
What you'll do
- Perform initial power-on and bringup of new silicon tape-outs, including boot sequence validation, clock/power domain verification, and initial functionality tests.
- Perform functional and electrical characterization of high-speed SerDes interfaces, photonic control blocks, and mixed signal blocks by defining and executing test plans at block and chip levels.
- Operate lab test equipment (BERT, oscilloscope/DCA, OSA, signal generators) to characterize signal integrity, eye diagrams, BER, jitter, and optical performance metrics.
- Develop and maintain Python-based test scripts and automation frameworks for regression and characterization testing.
- Investigate silicon anomalies and failures, collaborating with design and firmware engineers to develop and verify fixes.
- Author test plans, validation reports, and signoff documentation across the product development cycle.
What you'll need
- Bachelor's degree in Electrical Engineering or related field with 3+ years of relevant industry experience.
- Hands-on experience with post-silicon bringup and validation of high-speed SoC or mixed-signal devices.
- Working knowledge of SerDes PHY operation and characterization, including NRZ and/or PAM-4 signaling.
- Proficiency with lab equipment used for high-speed characterization, including BERT, oscilloscopes, and signal analyzers.
- Proficiency in Python for test scripting and data analysis.
- Proficiency with version control (Git) and software development environments.
Nice to have
- Experience with photonic device or electro-optic system characterization and validation.
- Familiarity with optical measurement equipment, including OSA, optical power meters, and lasers.
- Experience with high-speed serial standards: Ethernet (100G+), PCIe, or OIF CEI.
- Experience with board-level debug and hardware bring-up using JTAG or I2C/SPI interfaces.
More semiconductor jobs: Test engineer jobs · San Jose jobs
This role has been open 156 days — well above the 124-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
165
|
Median days open
124 d
|
Category median salary (all employers)
$138k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ayar Labs | All employers we track in this specialty (165 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 165 |
| Open roles in the wider Silicon Validation & Test family | 13 | 2395 · 121 employers |
| Median days open | 156 d | 124 d (+32 d vs this employer) |
| Median salary (USD postings) | — | $138k |
Who's hiring in this category
- Infineon Technologies · 11 open roles · median 111 d
- Qualcomm · 10 open roles · median 120 d
- Renesas Electronics · 10 open roles · median 118 d
- Marvell Technology · 9 open roles · median 136 d
- Teradyne · 9 open roles · median 139 d
- Texas Instruments · 8 open roles · median 119 d
How we counted: 165 open Silicon Test Engineering (Silicon Validation) roles from 54 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.