Sr. Engineer, Ethernet IP - Santa Clara, California, United States
$100,000 - $500,000 USD yearly
Originally posted 30 April 2025 by the employer — open 498 days.
About the role
This role involves deep-tech at the intersection of silicon development, low-level firmware, and high-speed networking.
What you'll do
- Develop and maintain low-level firmware to manage Ethernet MAC, PHY, and SerDes components.
- Drive silicon bring-up and validation of networking subsystems in the lab.
- Implement and optimize link-training algorithms and auto-negotiation protocols.
- Work with silicon architects to influence the design of networking hardware from a firmware perspective.
- Debug complex hardware-software interactions, including signal integrity issues and protocol-level timing bugs.
What you'll need
- Debug a link-training state machine.
- Understand the inner workings of Ethernet hardware (MAC/PHY/PCS) and how to control it efficiently via bare-metal firmware.
- Enjoy the "detective work" of hardware bring-up, using oscilloscopes or logic analyzers.
- Speak the languages of both the RTL team and the Network Software team, translating hardware constraints into software requirements.
Skills: embedded systems, silicon validation, SerDes tuning, Ethernet MAC/PHY, link training
This role has been open 180 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 180 d | 91 d (+89 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: embedded systems, silicon validation, SerDes tuning, Ethernet MAC/PHY, link training
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.