Sr. Debug Engineer - PCIe/CXL, RAS, Memory - TX, Austin, United States
Originally posted 28 October 2026 by the employer.
About the role
As a debug engineer on the Server Customer Engineering team, you will resolve customer issues and deliver root cause solutions for server platforms. The focus encompasses silicon and system-level debug across RAS, PCIe, CXL, and memory subsystems.
What you'll do
- Work on RAS, PCIe, Memory, MCA, CXL, and Micro-Controller related failures with customers to resolve issues. - Utilize debug tools, including debug scripts, protocol analyzers, SCAN, and JTAG tools, to narrow down and root cause customer failures. - Debug issues found during the process, bring-up, validation, and production phases of SOC programs. - Provide validation and debug recommendations to customers regarding validation, new features, and debug-related questions. - Collaborate with global cross-functional software, hardware, and design teams, leading task forces to resolve complex issues.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. - Silicon and system engineering expertise applied to customer enablement, debug, and root cause resolution. - Experience with debug tools such as protocol analyzers, SCAN, and JTAG tools. - Experience debugging issues across SOC bring-up, validation, and production phases.
Nice to have
- 10+ years of total experience in post silicon validation and debug methodologies. - Experience with RAS (reliability, availability and serviceability) validation and debug, or MCA/MCE (Machine check architecture and exception) validation and debug. - Experience in PCIe/CXL functional and protocol (e.g. Gen1~Gen6) debug, including PCIe/CXL IP bring up, validation, and analysis. - Experience in memory functional and protocol validation or debug. - Knowledge of X86 micro architecture. - Programming and scripting skills in Python, C++, Perl, or Ruby. - Experience handling high-speed test and measurement equipment such as scopes and protocol analyzers.
This role has been open 0 days — well below the 42-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
427
|
Median days open
42 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (427 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 57 | 427 |
| Open roles in the wider Silicon Validation & Test family | 146 | 2325 · 114 employers |
| Median days open | 43 d | 42 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Who's hiring in this category
- AMD (this employer) · 51 open roles · median 42 d
- Qualcomm · 37 open roles · median 29 d
- Micron Technology · 36 open roles · median 43 d
- NVIDIA · 24 open roles · median 28 d
- Microchip Technology · 22 open roles · median 79 d
- Apple · 21 open roles · median 5 d
How we counted: 427 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.