Spe Signal Integrity Engineer - United States
$133,900 USD yearly
Originally posted 3 August 2026 by the employer — open 38 days.
This role focuses on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the DDR field with speeds up to 12800+ MT/s.
About the role
This role involves the signal integrity and package design of memory interface chips. You will work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the DDR field with speeds up to 12800+ MT/s.
What you'll do
- Create SI/PI methodologies and perform SI/PI studies and package design for DDR product portfolios.
- Define specifications and system design requirements including packaging, PCB routings, IC-PKG-BRD decoupling, channel simulations, and jitter sensitivity analysis.
- Provide design guidelines based on SI/PI studies, simulations, and silicon correlation to optimize SI performance.
- Collaborate with customers to find optimum SI/PI solutions.
- Assist with debug and bring-up in the lab.
What you'll need
- MS or PhD in Electrical Engineering with 10+ years of industry experience, including DDR4/5 exposure.
- Prior experience simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces.
- Solid theoretical background and understanding in EM and transmission line theory.
- Strong background and understanding of equalization techniques such as FIR/FFE/DFE/CTLE.
- Understanding of package and PCB design, ability to edit APD/Allegro layout files, knowledge of SI/PI driven BGA assignment methodology, and ability to simulate trade-offs in a system context.
- Extensive experience correlating simulation results with lab measurements using scopes, TDRs, and VNAs.
- Proficient with simulations using Spice and ADS.
Nice to have
- Strong understanding of the server system, from CPUs to DRAMs on DIMM modules.
- Knowledge of crosstalk and jitter mechanisms in source-synchronous interfaces and ability to include their effects into low BER simulations.
- Familiarity with commercial EDA tools such as RedHawk/Totem or XcitePI and Virtuoso.
- Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR.
- Basic knowledge of circuits used in high-speed link design.
Skills: SI/PI, DDR4/DDR5, SerDes, EM theory, transmission line theory, package/PCB design
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Rambus | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 3 | 217 |
| Median days open | 153 d | 91 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI/PI, DDR4/DDR5, SerDes, EM theory, transmission line theory, package/PCB design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.