Software Engineer, Hardware Tools and Methodology - New College Grad 2026
$116,000 - $218,500 USD yearly
Originally posted 3 June 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
This role focuses on developing software tools, algorithms, and automated workflows for RTL generation across NVIDIA products. You will work within the NVIDIA Clocks team, applying both software and hardware principles to chip design infrastructure.
What you'll do
- Architect, design, develop, and support tools for RTL generation across all NVIDIA products.
- Architect automated workflows for supporting deliverables to multiple cross functional teams.
- Improve algorithms in C++ for automated connectivity, auto logic insertion, and post processing Verilog RTL.
- Improve the quality of existing tools and flows used by the team.
What you'll need
- Master's degree or higher in Computer Engineering or Electrical Engineering (or equivalent experience).
- Coding skills in C++.
- Understanding of ASIC Design and understanding of Verilog RTL.
- Experience working across multi-functional teams.
Skills: RTL generation, automated workflows, C++, Verilog RTL, ASIC Design
More semiconductor jobs: NVIDIA jobs · EDA tools engineer jobs · California jobs
This role has been open 149 days — well above the 60-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
717
|
Median days open
60 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (717 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 717 |
| Open roles in the wider Physical Implementation family | 97 | 1547 · 111 employers |
| Median days open | 122 d | 60 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL generation, automated workflows, C++, Verilog RTL, ASIC Design
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 156 d
- Synopsys · 58 open roles · median 47 d
- Micron Technology · 47 open roles · median 44 d
- Renesas Electronics · 37 open roles · median 8 d
- Keysight Technologies · 34 open roles · median 86 d
- Qualcomm · 34 open roles · median 81 d
How we counted: 717 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.