Physical Design Engineer
$150,400 - $225,300 USD yearly
About the role
This role involves collaborating on pad ring, bump, and RDL designs, performing various physical verification checks, and driving signoff closure for tape out throughout the chip design cycle.
What you'll do
- Collaborate with package and floorplan teams on pad ring, bump, and RDL designs.
- Perform various physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at chip and block levels.
- Interface with CAD/Technology teams for flow bring up and validation.
- Drive signoff closure for tape out by supporting schedules and cross-functional engineering efforts.
- Configure, review, and provide timely feedback on full chip DRC, LVS, PERC, and other full chip physical verification analysis.
- Work with the physical design team to drive methodologies and streamline physical design work, including guidelines and checklists.
- Resolve design and flow issues related to physical design, identify solutions, and drive execution.
What you'll need
- Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in physical design or related occupation.
- 2 years of experience with DRC debug, including Calibre DRC, for custom, analog, and digital physical design data.
- 2 years of experience with LVS debug, including Calibre LVS, for custom, analog, and digital physical design data.
- 2 years of experience with CMOS layout design using tools like Cadence Virtuoso, including bumps and RDL.
- Experience and/or education with PNR/APR implementation using tools like Cadence Innovus.
- Experience and/or education with Tcl/Perl/Python script development to facilitate design, verification, and signoff of physical design data.
Skills: physical verification, DRC debug, LVS debug, CMOS layout design, PNR/APR implementation
More semiconductor jobs: Physical design jobs
This role has been open 29 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
693
|
Median days open
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (693 roles · 84 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 693 |
| Open roles in the wider Physical Implementation family | 29 | 1547 · 111 employers |
| Median days open | 9 d | 59 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical verification, DRC debug, LVS debug, CMOS layout design, PNR/APR implementation
Who's hiring in this category
- Qualcomm · 111 open roles · median 52 d
- AMD · 63 open roles · median 33 d
- Synopsys · 40 open roles · median 45 d
- Broadcom · 38 open roles · median 100 d
- NVIDIA · 37 open roles · median 70 d
- Intel Corporation · 36 open roles · median 22 d
How we counted: 693 open Physical Design (Physical Design) roles from 84 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.