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Broadcom

Physical Design Engineer

Broadcom USA-CA San Jose Innovation Drive, United States Full-time 5 hours ago
Physical Design & EDA

$82,500 USD yearly

Originally posted 31 October 2026 by the employer.

About the role

Broadcom’s ASIC Products Division (APD) is looking for a Physical Design Engineer to join the Physical Design team executing implementation tasks for high-performance networking, AI/ML accelerators, and custom cloud ASICs. The role focuses on block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across sub-micron nodes including N5, N3, N2, and A14.

What you'll do

  • Participate in block-level floorplanning and run placement and route (P&R) flows using industry-standard EDA tools.
  • Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
  • Run Physical Verification checks including DRC, LVS, ERC, and Antenna, and resolve signoff violations.
  • Analyze IR drop and electromigration (EM) to ensure power grid integrity.
  • Develop and maintain automated scripts in TCL, Python, or Ruby to enhance flow efficiency and productivity.

What you'll need

  • Bachelor's degree in Electrical Engineering or Computer Engineering plus 2 years of experience, or a Master’s degree in Electrical Engineering or Computer Engineering with a graduation date within the past 12 months.
  • Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
  • Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
  • Coursework, lab experience, or academic projects using EDA design tools such as Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools.
  • Scripting proficiency in TCL, Python, Ruby, or Bash.

Nice to have

  • Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
  • Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.

More semiconductor jobs: Broadcom jobs · Physical design jobs

Market context

This role has been open 0 days — well below the 59-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
693
Median days open
59 d
Category median salary (all employers)
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How Broadcom compares in Physical Design hiring
Metric Broadcom All employers we track in this specialty (693 roles · 84 employers)
Open roles in this specialty 45 693
Open roles in the wider Physical Implementation family 52 1537 · 112 employers
Median days open 67 d 59 d (+8 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 111 open roles · median 52 d
  • AMD · 63 open roles · median 33 d
  • Synopsys · 40 open roles · median 45 d
  • Broadcom (this employer) · 38 open roles · median 100 d
  • NVIDIA · 37 open roles · median 70 d
  • Intel Corporation · 36 open roles · median 22 d

How we counted: 693 open Physical Design (Physical Design) roles from 84 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
USA-CA San Jose Innovation Drive, United States
On-site
Full-time
$82,500 USD yearly
5 hours ago

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