Software Engineer, Chip Design - Palo Alto, United States
Originally posted 10 September 2026 by the employer.
About the role
As a Software Engineer at Ricursive Intelligence, you will build the systems and infrastructure that power the chip design flow across the broader design stack.
What you'll do
- Develop and scale the infrastructure behind the chip design flow to support hierarchical design, advanced process nodes, and complex design constraints. - Analyze design metrics including timing violations, congestion, and routing issues to help the flow converge faster toward better PPA. - Deploy AI-driven methods to automate design analysis, optimization, and iteration across the flow. - Build reliable execution infrastructure, connect stages of the flow, and resolve scale-dependent issues across quality, runtime, and robustness constraints.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field. - Strong programming skills in Python, C++, Java, or a comparable language. - Working understanding of the digital chip design flow, including major stages from RTL through physical design and signoff. - Demonstrated ability to take ownership of ambiguous technical problems, ramp quickly in unfamiliar areas, and drive work through to production.
Nice to have
- Master’s or PhD in Computer Science, Electrical Engineering, or a related technical field. - Experience with semiconductor design, distributed systems, or optimization. - Familiarity with design automation algorithms in one or more areas of the chip design flow, such as placement, timing analysis, RC extraction, or netlist processing. - Demonstrated and quantified PPA benefit of using AI/ML tooling.
Skills: chip design flow, EDA tooling, PPA optimization, Python, C++
This role has been open 1 day — well below the 33-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
72
|
Median days open
33 d
|
Median salary
$209k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ricursive Intelligence | All employers we track in this specialty (72 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 72 |
| Open roles in the wider Physical Implementation family | 4 | 1530 · 112 employers |
| Median days open | 1 d | 33 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $209k |
Skills observed across this category: chip design flow, EDA tooling, PPA optimization, Python, C++
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 75 d
- NVIDIA · 8 open roles · median 33 d
- Keysight Technologies · 7 open roles · median 27 d
- Synopsys · 6 open roles · median 10 d
- Cadence Design Systems · 5 open roles · median 80 d
- Qualcomm · 4 open roles · median 27 d
How we counted: 72 open EDA/CAD Engineering (AI EDA Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.