SoC Timing (Static Timing Analysis/STA) Engineer, HBM - Richardson, TX, United States

Originally posted 14 May 2026 by the employer.

High Bandwidth Memory (HBM) solutions utilizing Through Silicon Via (TSV) technology and multi-die DRAM stacking.

About the role

As a Static Timing Analysis (STA) Engineer in the Heterogeneous Integration Group (HIG), you will own chip-level timing sign-off across all modes and corners from initial design through tape-out. The role focuses on High Bandwidth Memory (HBM) solutions utilizing Through Silicon Via (TSV) technology and multi-die DRAM stacking.

What you'll do

- Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage/temperature conditions. - Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. - Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, engineering change orders (ECOs), and close collaboration with physical design on placement, clock tree synthesis, and routing. - Perform multi-mode, multi-corner (MMMC) analysis including clock domain crossing timing, on-chip variation (OCV, AOCV, POCV), and advanced-node timing methodologies. - Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and partner with physical design teams on mitigation strategies. - Build and maintain static timing analysis automation and flows using Python and Tcl for reporting, regression tracking, quality of results dashboards, and sign-off readiness.

What you'll need

- 10+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below. - Deep expertise with industry-standard static timing analysis tools such as Synopsys PrimeTime and/or Cadence Tempus. - Expert understanding of advanced timing concepts including multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing. - Proven ability to develop and manage complex hierarchical SDC constraints for large systems on chip with multiple clock and power domains. - Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.

Nice to have

- Experience with high-bandwidth memory (HBM), dynamic random-access memory (DRAM), or memory-centric system-on-chip designs. - Exposure to design for test timing, including scan, memory built-in self-test (MBIST), and Joint Test Action Group (JTAG) interfaces. - Experience with chiplet-based or three-dimensional integrated circuit designs and die-to-die interface timing methodologies. - Familiarity with foundry process design kits, Liberty timing models, and advanced noise and variation modeling. - Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

Skills: static timing analysis, Synopsys PrimeTime, SDC, timing closure, HBM