SoC Principal Physical Design Engineer
Lead full-chip and block-level RTL-to-GDSII physical implementation at 5nm, 3nm, and below using Fusion Compiler, PrimeTime, and StarRC.
Originally posted 1 November 2026 by the employer.
About the role
The SoC Principal Physical Design Engineer leads full-chip and block-level physical implementation from RTL through GDSII tapeout on advanced-node designs at 5nm, 3nm, and below.
What you'll do
- Define and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies to achieve PPA targets.
- Drive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler, PrimeTime, and StarRC.
- Perform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification using IC Validator.
- Work directly with semiconductor customers to troubleshoot design challenges and deliver technical workshops and methodology guidance.
- Develop automation scripts and flows using Python, Tcl, and shell scripting to improve design productivity and methodology efficiency.
- Leverage AI and ML-based physical design technologies, including DSO.ai and Fusion Compiler optimizations, to explore the design space.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 10 to 15+ years of hands-on ASIC or SoC physical design experience with multiple successful tapeouts at advanced process nodes.
- Deep expertise in floorplanning, power planning, place and route, clock tree synthesis, timing closure, and physical verification including DRC and LVS.
- Strong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage design fixes.
- Proficiency in scripting languages including Python, Tcl, Perl, or shell for automation and flow development.
Nice to have
- Experience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality, and PrimePower.
- Familiarity with foundry technologies from TSMC, Samsung, or Intel and an understanding of process characteristics at 5nm and below.
Skills: floorplanning, CTS, timing closure, PrimeTime, Fusion Compiler, StarRC
More semiconductor jobs: Synopsys jobs · Physical design jobs · Austin jobs
This role has been open 0 days — well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
684
|
Median days open
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (684 roles · 83 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 684 |
| Open roles in the wider Physical Implementation family | 108 | 1559 · 110 employers |
| Median days open | 33 d | 62 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: floorplanning, CTS, timing closure, PrimeTime, Fusion Compiler, StarRC
Who's hiring in this category
- Qualcomm · 107 open roles · median 54 d
- AMD · 60 open roles · median 34 d
- Broadcom · 45 open roles · median 69 d
- NVIDIA · 42 open roles · median 78 d
- Synopsys (this employer) · 36 open roles · median 37 d
- Intel Corporation · 32 open roles · median 24 d
How we counted: 684 open Physical Design (Physical Design) roles from 83 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.