Layout Design Intern

About the role

This position requires the creation and management of integrated circuit (IC) layouts from start to finish, using CAD software to floorplan, design, implement, and verify analog integrated circuits. You will develop multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and geometry provided by design engineering.

What you'll do

• Collaborate with Analog and Digital design teams and the global layout design community.
• Floorplan, design, implement, and verify analog integrated circuits while addressing precision, speed, area, reliability, power, and ESD requirements.
• Write layout specifications, check dimensions, and verify completed art work.
• Verify that layouts comply with Design Rule Checks (DRCs) and Electrical Rule Checks (ERCs).
• Work with PE/Packaging engineers to assure reliable production capability and proper data preparation for fab hand-off, documentation, and archive.
• Participate in layout design reviews and create design flow automation.

What you'll need

• Currently pursuing an Associates or Bachelors degree in Electrical Engineering, Engineering Technology, or a related degree.
• Minimum 3.0 out of 4.0 GPA.

Nice to have

• Working knowledge of electrical circuits such as resistance, capacitance, voltage, and current.
• Familiarity with Unix/Linux, Cadence Virtuoso, Assura LVS, DRC, or similar mixed signal EDA tools (Mentor, Synopsys).
• Basic proficiency in one or more coding languages such as Perl, Python, C, or Cadence SKILL.
• Familiarity with semiconductor device physics, analog circuits, and their layout sensitivities.
• Working knowledge of semiconductor processes and IC production flow including BJTs, Diodes, FETs, passive components, packaging, and thermal design.
• Working knowledge of layout-related matching techniques, on-chip parasitic sources and minimization, routing impedances, electromigration, and crosstalk.

Skills: Cadence Virtuoso, DRC, LVS, IC layout, analog circuits

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