Layout Engineer, Power Modules - Bangalore, Karnataka, India
Originally posted 1 October 2026 by the employer.
Design silicon interposer and power-module layouts.
About the role
This role involves designing silicon interposer and power-module layouts, and transforming design practices into layout-authoring capabilities on an internal engineering platform. The scope covers the full path from floorplan and PDK-based layout through verification and tapeout.
What you'll do
- Design and edit power-module and silicon-interposer layouts, including die placement, power and signal routing, pads, and top-level assembly using PDK and IP views.
- Own assigned module layouts from floorplan through implementation, ensuring traceability across variants and revisions.
- Run and interpret DRC, LVS, and parasitic extraction, using results to correct layout.
- Prepare layouts for design release, including stream-out, database transfer, and tapeout evidence.
- Use KLayout for layout review and scripted edits, extending this workflow to Cadence Virtuoso and other power-module development tools.
- Identify tool actions an AI agent needs to create, edit, inspect, and check layouts, including required inputs, safe bounds, and expected outputs.
What you'll need
- 4 to 8 years of hands-on IC or power-module layout experience, including released or tapeout-ready work.
- Strong Cadence Virtuoso Layout experience, including Layout XL, schematic-driven layout, and PDK or PCell-based design.
- Practical use of Siemens Calibre for DRC and LVS, and working knowledge of PEX or another parasitic-extraction flow.
- Understanding of how floorplan, placement, routing, pads, and top-level assembly affect resistance, loop inductance, current density, and thermal behavior in a power module.
- Experience taking a layout through stream-out and database transfer, with familiarity with Cliosoft SOS or an equivalent design-data system.
- Ability to inspect GDS or OASIS and make controlled edits with KLayout, Calibre DESIGNrev, or equivalent layout tooling.
- Enough Python or SKILL to automate repetitive layout, query, or checking tasks, and explain manual tool actions for software engineers.
- Careful review of generated layout against design intent, design rules, and connectivity.
Nice to have
- Layout experience with SiC or other wide-bandgap multi-die power modules, silicon interposers, or heterogeneous integration.
- Familiarity with the onsemi power-module flow across die, interposer, package, and system, including Ansys Q3D, R3D, and thermal or mechanical checks driven by layout.
- Experience with Virtuoso SKILL, Python layout APIs, or batch verification flows.
- Exposure to pads and ESD, bonding-diagram generation, reticle or database release, and fab or process feedback.
- Interest in AI-assisted layout, AI agent tool use, or reviewing AI-generated engineering output.
- Experience contributing design-rule, PDK, or layout-review knowledge to an internal platform or automation project.
Skills: silicon interposer, power-module layouts, floorplan, PDK-based layout, DRC, LVS, Cadence Virtuoso
This role has been open 0 days — well below the 160-day median for Physical Design roles.
Physical Design · Digital Backend
|
Open roles in category
37
|
Median days open
160 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (37 roles · 22 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 37 |
| Open roles in the wider Physical Implementation family | 9 | 1427 · 109 employers |
| Median days open | 0 d | 160 d (−160 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: silicon interposer, power-module layouts, floorplan, PDK-based layout, DRC, LVS
Who's hiring in this category
- Micron Technology · 5 open roles · median 159 d
- Qualcomm · 3 open roles · median 153 d
- AMD · 2 open roles · median 121 d
- Analog Devices · 2 open roles · median 182 d
- Lightmatter · 2 open roles · median 199 d
- Microchip Technology · 2 open roles · median 197 d
How we counted: 37 open Physical Design (Digital Backend) roles from 22 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.