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Qualcomm

SoC Physical Design Engineer (Senior/Lead) - Bangalore, India

Qualcomm Bangalore, India 17 days ago
Physical Design & EDA

Originally posted 18 September 2026 by the employer — open 0 days.

About the role

This role involves end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.

What you'll do

  • Own end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.
  • Drive Floorplanning, Power Planning (PDN), Placement, CTS, Routing, STA, and Timing Closure.
  • Perform physical verification including DRC, LVS, and signoff checks.
  • Collaborate with RTL, STA, DFT, Verification, and CAD teams.
  • Debug and resolve timing, congestion, IR drop, and physical design challenges.
  • Support successful chip tapeouts on advanced technology nodes.

What you'll need

  • 3-6 years of hands-on experience in SoC/ASIC Physical Design.
  • Expertise in Floorplanning, PDN, Placement, CTS, Routing, and Timing Closure.
  • Experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, and Calibre.
  • Understanding of physical verification, power integrity, and signoff methodologies.
  • Experience working on advanced nodes (16nm and below).

Nice to have

  • Experience in high-performance CPU, GPU, AI, Mobile, Networking, or Multimedia SoCs.

Skills: Floorplanning, Power Planning, Placement, CTS, Routing, STA, Timing Closure, DRC, LVS

Market context

This role has been open 0 days — well below the 57-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
601
Median days open
57 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Qualcomm compares in Physical Design hiring
Metric Qualcomm All employers we track in this specialty (601 roles · 78 employers)
Open roles in this specialty 112 601
Open roles in the wider Physical Implementation family 155 1388 · 105 employers
Median days open 40 d 57 d (−17 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: Floorplanning, Power Planning, Placement, CTS, Routing, STA

Who's hiring in this category

  • Qualcomm (this employer) · 103 open roles · median 42 d
  • Broadcom · 38 open roles · median 67 d
  • NVIDIA · 38 open roles · median 48 d
  • AMD · 34 open roles · median 41 d
  • Synopsys · 28 open roles · median 57 d
  • Renesas Electronics · 25 open roles · median 44 d

How we counted: 601 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

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Bangalore, India
On-site
17 days ago

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