SoC Lead Engineer – LEC & Low Power Signoff - ON, Markham-33CV, Canada
Originally posted 28 September 2026 by the employer.
About the role
This role involves driving Low Power Static Verification and Logical Equivalence Check (LEC) signoff as part of SoC development efforts, covering full-chip and block-level designs.
What you'll do
- Lead and own the full LEC signoff chain from RTL to physical netlist (RTL, post-synthesis netlist, post-DFT netlist, post-floorplan netlist, and post-P&R (GDS-level) netlist).
- Drive full-chip top-level and tile-level low power static checks across all stages of the SoC design flow.
- Debug and resolve logical equivalence and low power static check issues in synthesis and place-and-route flows.
- Lead a small team, owning task delivery, milestone tracking, and issue resolution.
- Guide team members on LEC strategy and track design changes across project phases.
What you'll need
- Proven experience in SoC implementation and tapeout.
- Demonstrated leadership owning and driving LEC and low power static verification to completion.
- In-depth expertise in Logical Equivalence Check (LEC) and Low Power Static Verification.
- Strong understanding of and hands-on coding experience in Verilog and VHDL.
- Hands-on with Synopsys Formality and/or Cadence Conformal for LEC.
- Hands-on with Synopsys VC-LP (preferred) or Cadence Conformal Low Power (CLP) for Low Power Static Signoff.
- Hands-on with Design Compiler / Fusion Compiler for Synthesis.
- Hands-on with PrimeTime for Static Timing Analysis (STA).
- Solid understanding of low power design and UPF-based methodology, including UPF implementation and evolution across Synthesis and Place-and-Route (PnR) flows.
- Strong scripting skills (Tcl, Perl, Python).
- BS/MS in Electrical Engineering, ECE, EEE, or related field.
Nice to have
- Hands-on with IC Compiler II / Fusion Compiler for Place & Route.
Skills: LEC signoff, low power static verification, UPF methodology, Synopsys Formality, Fusion Compiler
This role has been open 1 day — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
627
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (627 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 43 | 627 |
| Open roles in the wider Physical Implementation family | 70 | 1420 · 109 employers |
| Median days open | 28 d | 64 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: LEC signoff, low power static verification, UPF methodology, Synopsys Formality, Fusion Compiler
Who's hiring in this category
- Qualcomm · 114 open roles · median 40 d
- AMD (this employer) · 44 open roles · median 28 d
- Broadcom · 40 open roles · median 78 d
- NVIDIA · 38 open roles · median 53 d
- Synopsys · 27 open roles · median 56 d
- NXP Semiconductors · 25 open roles · median 77 d
How we counted: 627 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.