SoC High-Speed Interface Architect - Bangalore (India), India

Originally posted 19 August 2026 by the employer.

About the role

This SoC architecture role focuses on the chip-level integration of high-speed interface PHYs on an automotive microcontroller platform.

What you'll do

• Own the SoC-level integration architecture for high-speed interface PHYs, defining placement strategy, power delivery, reference clock assignment, and electrical compliance requirements.
• Define and maintain chip-level interface specifications for high-speed PHY IP teams, including jitter budgets, termination requirements, and signal integrity constraints.
• Serve as the primary SoC architecture interface to PHY IP teams and external PHY vendors, driving integration feasibility assessments and resolving chip-level signal integrity issues.
• Perform or oversee early signal integrity simulation and parasitic analysis for high-speed interface regions of the chip.
• Review and provide architectural sign-off on PHY IP integration results, floorplan proposals, and high-speed IO region design decisions.
• Maintain technical architecture documentation in compliance with ISO 26262 requirements.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering or related field.
• At least 10 years of industry experience in semiconductor development with proven experience in high-speed interface architecture or integration.
• Strong knowledge of high-speed interface PHYs: LPDDR memory PHY, Ethernet PHY, and high-speed serial interfaces (HSPHY/SerDes).
• Experience with chip-level signal integrity, jitter budgets, and eye diagram analysis for high-speed interfaces.
• Understanding of PHY placement constraints, power delivery requirements, and reference clock architecture for high-speed interfaces.
• Familiarity with IO ring architecture and ESD protection strategy at high-speed IO boundaries.
• Familiarity with ISO 26262 documentation standards.

Nice to have

• Owned chip-level integration architecture for LPDDR, Ethernet PHY, or high-speed SerDes in a previous SoC program.
• Defined jitter budgets, power delivery specs, and placement constraints for high-speed PHYs at the SoC level.
• Worked with PHY IP vendors to establish interface specifications, simulation models, and integration acceptance criteria.
• Experience distinguishing SoC-level integration constraints from IP-internal design decisions.
• Contributed to datasheet electrical parameters for high-speed interface sections.

Skills: high-speed interface PHYs, LPDDR, Ethernet PHY, SerDes, signal integrity, jitter budgets, ISO 26262