SoC Design Verification Engineer - California, Santa Clara, United States
$105,650 - $172,860 USD yearly
Originally posted 14 August 2026 by the employer. Relisted by the employer on 20 October 2026.
Join the Server SoC Design Validation team working on Xeon server product SOCs and IPs.
About the role
This role sits within the Server SoC Design Validation team, focusing on functional verification and emulation validation for Xeon server product SOCs and IPs.
What you'll do
- Perform functional logic verification and emulation validation of integrated SoCs to ensure designs meet microarchitecture specifications. - Define, develop, and maintain block, subsystem, and SoC verification plans, testbenches, and verification environments. - Execute verification plans and run emulation and system simulation models to verify designs, analyze power and performance, and identify bugs. - Replicate, root-cause, and debug failing tests within the pre-silicon environment, implementing corrective measures. - Collaborate with SoC architects, micro-architects, RTL developers, and physical design teams to document test plans and conduct technical reviews. - Incorporate security activities within test plans, execute regression and debug suites, and apply post-silicon learnings to improve pre-silicon coverage closure.
What you'll need
- Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field. - 10+ months of experience with silicon design and/or validation/verification. - 10+ months of experience with x86 architecture. - 10+ months of design and validation experience with global domains such as Reset, Clock, Fuse, GPIO, or MPP.
Nice to have
- Experience with UVM/SV constrained-random coverage-based design verification and formal verification methodology. - Working knowledge of cache coherency principles in multi-processor SOCs and layered protocols (transaction layer, data link layer, PHY layer). - Experience across the complete verification life cycle, including verification architecture, test planning, execution, debug, and coverage closure. - Experience with Xeon CPU pre-silicon, emulation validation, or post-silicon validation. - Proficiency in one or more scripting languages for automation.
Skills: functional logic verification, SoC verification plans, UVM/SV, constrained random, coverage closure, pre-silicon debug
This role has been open 67 days — slightly above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1214
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1214 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 33 | 1214 |
| Open roles in the wider Digital Design & Verification family | 89 | 3244 · 116 employers |
| Median days open | 34 d | 64 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: functional logic verification, SoC verification plans, UVM/SV, constrained random, coverage closure, pre-silicon debug
Who's hiring in this category
- Qualcomm · 113 open roles · median 40 d
- AMD · 96 open roles · median 53 d
- NVIDIA · 84 open roles · median 61 d
- Synopsys · 65 open roles · median 35 d
- SiFive · 55 open roles · median 77 d
- Cadence Design Systems · 50 open roles · median 119 d
How we counted: 1214 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.