Lead formal verification methodology, ISA formalization, and infrastructure for GFXIP designs.
Originally posted 8 May 2026 by the employer. Relisted by the employer on 6 November 2026.
About the role
AMD is hiring an SMTS Silicon Design Engineer to lead research and strategy for formal verification domains across graphics IP design.
What you'll do
- Lead research in emerging formal verification domains including security, safety, low-power, and architectural-level verification.
- Explore the feasibility of formalizing ISA and memory models for GFXIP design.
- Define long-term strategy and technical roadmaps for formal verification across the graphics design IP development lifecycle.
- Develop formal verification methodologies covering datapath and control logic, scaling verification to large, critical designs.
- Resolve convergence issues using techniques such as induction, reduction, and abstraction.
- Lead definition, design, verification, and documentation for ASIC development while evaluating process flows across synthesis, place and route, timing, and power.
What you'll need
- Master’s degree in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field with 4 years of engineering experience (or a Bachelor’s degree with 6 years of progressive experience).
- 4 years of experience with formal verification of algorithms, engines, and use cases.
- 4 years of experience with SystemVerilog Assertion and abstract model development.
- 4 years of experience using formal verification tools such as JasperGold, VC Formal, Murphi, or theorem provers.
- 4 years of experience delivering verification for large-scale processor designs such as CPU, GPU, or AI processors.
- 4 years of experience with computer architecture, graphics pipelines, and developing formal verification infrastructure for FPV, DPV, SEV, and other use cases.
Skills: Scan Insertion, LBIST, MBIST, ATPG verification, ASIC Design, DFT architecture
More semiconductor jobs: AMD jobs · DFT engineer jobs · Texas jobs
This role has been open 182 days — well above the 53-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
284
|
Median days open
53 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (284 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 43 | 284 |
| Open roles in the wider Digital Design & Verification family | 277 | 3526 · 120 employers |
| Median days open | 45 d | 53 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: Scan Insertion, LBIST, MBIST, ATPG verification, ASIC Design, DFT architecture
Who's hiring in this category
- AMD (this employer) · 36 open roles · median 50 d
- Qualcomm · 24 open roles · median 76 d
- NVIDIA · 23 open roles · median 55 d
- Broadcom · 21 open roles · median 3 d
- NXP Semiconductors · 20 open roles · median 55 d
- Synopsys · 19 open roles · median 35 d
How we counted: 284 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.